diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-02-05 11:27:44 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-04-28 05:38:34 +0200 |
| commit | e976bd44692d2adb320a1256f1b6bfaa6469108a (patch) | |
| tree | 32321588165b81c5fd0c91c859b238df52086ee2 /src/southbridge | |
| parent | f748f83ecb389552e7afe10ce8837b5173534b96 (diff) | |
soc/intel/apollolake: Enable LPC bus interface
This adds early LPC setup in bootblock (for Chrome EC) as well as
late (ramstage) IO decode/sirq enable.
Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Freddy Paul <freddy.paul@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14469
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions