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authorMarc Jones <marc.jones@amd.com>2007-05-10 23:53:11 +0000
committerStefan Reinauer <stepan@openbios.org>2007-05-10 23:53:11 +0000
commitd03b7d428978ce53dc9aa5e7df6ada2f78c96c61 (patch)
treeb5b171881d3052e4b40af635bae6386736644995 /src/southbridge
parentdeabf510bff37c1f3a1fd3ec50b88db17d38b802 (diff)
This fix properly hides the UDC and OTG PCI headers when the cs5536 is
setup as the host on USB port4. In client mode the headers remain available. Also fixes an outb to 0x80 to use the post_code() function. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 653323619b..69427f5494 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -487,13 +487,13 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
if (dev) {
- pci_write_config8(dev, 0x7C, 0xDEADBEEF);
+ pci_write_config32(dev, 0x7C, 0xDEADBEEF);
}
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
if (dev) {
- pci_write_config8(dev, 0x7C, 0xDEADBEEF);
+ pci_write_config32(dev, 0x7C, 0xDEADBEEF);
}
}
@@ -512,7 +512,7 @@ void chipsetinit(void)
(struct southbridge_amd_cs5536_config *)dev->chip_info;
struct msrinit *csi;
- outb(P80_CHIPSET_INIT, 0x80);
+ post_code(P80_CHIPSET_INIT);
/* we hope NEVER to be in linuxbios when S3 resumes
if (! IsS3Resume()) */