diff options
| author | Susendra Selvaraj <susendra.selvaraj@intel.com> | 2016-06-22 03:52:03 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-28 23:06:10 +0200 |
| commit | ab88c7d36630db9583d1b9a602f0e293f0447f04 (patch) | |
| tree | 56e2b1b11a83b2e6b754e0330a6ec282ccfe2623 /src/southbridge | |
| parent | df12d1923f76576534bbdfe69e2fd56d9c820faf (diff) | |
google/reef: Write protect GPIO relative to bank offset
Update the write protect GPIO reported in ACPI to GPIO_75.
Also update the controller ID to "INT3452:01" which will
point at the goldmont device and includes write protect GPIO.
BUG=chrome-os-partner:55604
BRANCH=none
TEST=verify crossystem output for wpsw_cur.
Change-Id: Ibe6a013aaab18bfa2436698298177218ca934fab
Signed-off-by: Susendra Selvaraj <susendra.selvaraj@intel.com>
Reviewed-on: https://coreboot.intel.com/7929
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions