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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-14 01:19:36 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-16 08:05:02 +0000 |
| commit | 96cb2522fd05369f9ef58c782204b3ef0fd9749e (patch) | |
| tree | cd5cf03748113f83079bb2fa45bc0c8be9390636 /src/southbridge | |
| parent | 87e6796a90d1f1cadd5b4981d6f45388de96bd42 (diff) | |
sb/intel/i82801dx: Drop smm_setup_structures()
The only board that builds this does not have ACPI S3 support.
Also the code is wrong.
Change-Id: Ifb8e0ae5b6d862fa6a52b8e08197a84e7da4be36
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801dx/smi.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index d7a02ef8bd..fe4f864f4c 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -330,14 +330,3 @@ void aseg_smm_lock(void) printk(BIOS_DEBUG, "Locking SMM.\n"); northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); } - -void smm_setup_structures(void *gnvs, void *tcg, void *smi1) -{ - /* The GDT or coreboot table is going to live here. But a long time - * after we relocated the GNVS, so this is not troublesome. - */ - *(u32 *)0x500 = (u32)gnvs; - *(u32 *)0x504 = (u32)tcg; - *(u32 *)0x508 = (u32)smi1; - outb(0xea, 0xb2); -} |