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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 09:09:12 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:11:33 +0000 |
| commit | 5ac723e5a4a22bc9a08098cd59de5026b18d362d (patch) | |
| tree | 1dd12f2f9c99d90dddfb08da50d7cf46264fc716 /src/southbridge | |
| parent | b30fe36734df3c48ec35438052ee8b28bf7a6a44 (diff) | |
nb/intel: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions