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authorStefan Reinauer <stefan.reinauer@coreboot.org>2011-10-13 17:04:02 -0700
committerUwe Hermann <uwe@hermann-uwe.de>2011-10-15 13:40:17 +0200
commit328a694a3f2055c5e6a88ae51c9a8eefb61fd11c (patch)
treeb738e9265f3e2d86dd66d995a5f949982982394d /src/southbridge
parentab87254b6130d74f080e2c5ee9abb4570560e6a0 (diff)
AMD CPU and chipset fixes for compilation with gcc 4.6
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/266 Tested-by: build bot (Jenkins) Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/rs780/rs780.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index b8c7d04822..cf6d2dfb1a 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -190,7 +190,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
{
/* NB_InitGFXStraps */
u32 MMIOBase, apc04, apc18, apc24, romstrap2;
- msr_t pcie_mmio_save;
+ msr_t pcie_mmio_save = { 0, 0 };
volatile u32 * strap;
// disable processor pcie mmio, if enabled