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author | Thaminda Edirisooriya <thaminda@google.com> | 2015-08-26 12:22:29 -0700 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-08-26 23:50:45 +0000 |
commit | 31f0521a996791f842af94f0c561c18fd2aec2ba (patch) | |
tree | ee6e821d477aa2ae43a6c9106c088c35c190f71b /src/southbridge | |
parent | 5cd34e2f15e1bf562fa80f013995d77429ea784f (diff) |
riscv-trap-handling: Add preliminary trap handling for riscv
RISCV requires a trap handler at the machine stage to deal with
misaligned loads/stores, as well as to deal with calls that a linux
payload will make in its setup. Put required assembly for jumping
into and out of a trap here to be set up by the bootblock in a later
commit.
Change-Id: Ibf6b18e477aaa1c415a31dbeffa50a2470a7ab2e
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11367
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions