diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-04-20 22:23:56 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2011-04-20 22:23:56 +0000 |
| commit | 305f2f50abe0360b10f2fef3d65a102912dade40 (patch) | |
| tree | 0ba7f7e2606d87451d64b7658b4d956e0199dec3 /src/southbridge | |
| parent | 685ee37a12f66f57b76e4be28fc59b30faa666da (diff) | |
drop dead code from sb800 bootblock
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/cimx_wrapper/sb800/bootblock.c | 35 |
1 files changed, 1 insertions, 34 deletions
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c index 2136c348a6..629685d689 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c +++ b/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c @@ -21,39 +21,6 @@ #include <arch/io.h> #include <arch/romcc_io.h> - -#if CONFIG_CONSOLE_POST == 1 - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -#ifndef CONFIG_TTYS0_DIV -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) -#endif // CONFIG_TTYS0_DIV - -#define UART_LCS CONFIG_TTYS0_LCS - -#endif // CONFIG_CONSOLE_POST == 1 - - static void sb800_enable_rom(void) { u32 word; @@ -68,7 +35,7 @@ static void sb800_enable_rom(void) */ dword = pci_io_read_config32(dev, 0x44); //dword |= (1<<6) | (1<<29) | (1<<30) ; - /*Turn on all of LPC IO Port decode enable */ + /* Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); |