diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-05 10:42:20 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-07 14:19:34 +0000 |
| commit | 244a425efdd2b291ba4e347e4b79181212a5bf52 (patch) | |
| tree | d13c7804b72eac50e01628989dc8a53a32be3945 /src/southbridge | |
| parent | f47117134d0b19914eb266af2f4f8094ca7621e6 (diff) | |
sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
Testing shows that these registers are backwards. Use the definitions
from Broadwell instead. All affected boards use the same value for both.
Change-Id: Ie47c9fddc2e9e15ce4c64821ea3a69356ac31b1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 66cd05e66a..429dcc032b 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -267,10 +267,10 @@ void mainboard_config_rcba(void); /* SATA IOBP Registers */ #define SATA_IOBP_SP0G3IR 0xea000151 #define SATA_IOBP_SP1G3IR 0xea000051 -#define SATA_IOBP_SP0DTLE_DATA 0xea002550 -#define SATA_IOBP_SP0DTLE_EDGE 0xea002554 -#define SATA_IOBP_SP1DTLE_DATA 0xea002750 -#define SATA_IOBP_SP1DTLE_EDGE 0xea002754 +#define SATA_IOBP_SP0DTLE_DATA 0xea002750 +#define SATA_IOBP_SP0DTLE_EDGE 0xea002754 +#define SATA_IOBP_SP1DTLE_DATA 0xea002550 +#define SATA_IOBP_SP1DTLE_EDGE 0xea002554 #define SATA_DTLE_MASK 0xF #define SATA_DTLE_DATA_SHIFT 24 |