drop a lot of dead code, including an old winbond southbridge from our removed

ppc port, some ambiguous use of CONFIG_IDE and an unused ide driver (we dropped
the filesystems already to be used with it) (somewhat trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 0 insertions, 550 deletions

diff --git a/src/southbridge/winbond/w83c553/Config.lb b/src/southbridge/winbond/w83c553/Config.lb
deleted file mode 100644
index 8bc503fbf2..0000000000
--- a/src/southbridge/winbond/w83c553/Config.lb
+++ /dev/null
@@ -1,4 +0,0 @@
-#config chip.h
-#object w83c553f.o
-driver w83c553f.o
-driver w83c553f_ide.o
diff --git a/src/southbridge/winbond/w83c553/Kconfig b/src/southbridge/winbond/w83c553/Kconfig
deleted file mode 100644
index 4f28b2ea3c..0000000000
--- a/src/southbridge/winbond/w83c553/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-config SOUTHBRIDGE_WINBOND_W83C553
-	bool
diff --git a/src/southbridge/winbond/w83c553/Makefile.inc b/src/southbridge/winbond/w83c553/Makefile.inc
deleted file mode 100644
index ef1156822f..0000000000
--- a/src/southbridge/winbond/w83c553/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-driver-y += w83c553f.o
-driver-y += w83c553f_ide.o
diff --git a/src/southbridge/winbond/w83c553/chip.h b/src/southbridge/winbond/w83c553/chip.h
deleted file mode 100644
index 20a9a693ff..0000000000
--- a/src/southbridge/winbond/w83c553/chip.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _SOUTHBRIDGE_WINBOND_W83C553
-#define _SOUTHBRIDGE_WINBOND_W83C553
-
-extern struct chip_operations southbridge_winbond_w83c553_control;
-
-struct southbridge_winbond_w83c553_config {
-};
-
-#endif /* _SOUTHBRIDGE_WINBOND_W83C553 */
diff --git a/src/southbridge/winbond/w83c553/w83c553f.c b/src/southbridge/winbond/w83c553/w83c553f.c
deleted file mode 100644
index 8f70ff032b..0000000000
--- a/src/southbridge/winbond/w83c553/w83c553f.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Initialisation of the PCI-to-ISA bridge and disabling the BIOS
- * write protection (for flash) in function 0 of the chip.
- * Enabling function 1 (IDE controller of the chip.
- */
-
-#ifndef CONFIG_ISA_IO
-#define CONFIG_ISA_IO         0xFE000000
-#endif
-
-#include <arch/io.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "w83c553f.h"
-
-void initialise_pic(void);
-void initialise_dma(void);
-
-static void 
-w83c553_init(struct device *dev)
-{
-	printk_info("Configure W83C553F ISA Bridge (Function 0)\n");
-
-#if 0
-	/*
-	 * Set ISA memory space NOT SURE ABOUT THIS???
-	 */
-	reg8 = pci_read_config8(dev, W83C553F_IPADCR);
-	/* 16 MB ISA memory space */
-	reg8 |= (W83C553F_IPADCR_IPATOM4 | W83C553F_IPADCR_IPATOM5 | W83C553F_IPADCR_IPATOM6 | W83C553F_IPADCR_IPATOM7);
-	reg8 &= ~W83C553F_IPADCR_MBE512;
-	pci_write_config8(dev, W83C553F_IPADCR, reg8);
-
-	/*
-	 * Chip select: switch off BIOS write protection
-	 */
-	reg8 = pci_read_config8(dev, W83C553F_CSCR);
-	reg8 |= W83C553F_CSCR_UBIOSCSE;
-	reg8 &= ~W83C553F_CSCR_BIOSWP;
-	pci_write_config8(dev, W83C553F_CSCR, reg8);
-
-	/*
-	 * Enable Port 92
-	 */
-	reg8 = W83C553F_ATSCR_P92E | W83C553F_ATSCR_KRCEE;
-	pci_write_config8(dev, W83C553F_CSCR, reg8);
-
-	/*
-	 * Route IDE interrupts to IRQ 14 & 15 on 8259.
-	 */
-	pci_write_config8(dev, W83C553F_IDEIRCR, 0x90);
-	pci_write_config16(dev, W83C553F_PCIIRCR, 0xABEF);
-
-	/*
-	 * Initialise ISA interrupt controller
-	 */
-	initialise_pic();
-
-	/*
-	 * Initialise DMA controller
-	 */
-	initialise_dma();
-#endif
-
-	printk_info("W83C553F configuration complete\n");
-}
-
-void initialise_pic(void)
-{
-	outb(W83C553F_PIC1_ICW1, 0x11); /* start init sequence, ICW4 needed */
-	outb(W83C553F_PIC1_ICW2, 0x08); /* base address 00001 */
-	outb(W83C553F_PIC1_ICW3, 0x04); /* slave on IRQ2 */
-	outb(W83C553F_PIC1_ICW4, 0x01); /* x86 mode */
-	outb(W83C553F_PIC1_OCW1, 0xfb); /* enable IRQ 2 */
-	outb(W83C553F_PIC1_ELC, 0xf8);	/* all IRQ's edge sensitive */
-
-	outb(W83C553F_PIC2_ICW1, 0x11); /* start init sequence, ICW4 needed */
-	outb(W83C553F_PIC2_ICW2, 0x08); /* base address 00001 */
-	outb(W83C553F_PIC2_ICW3, 0x02); /* slave ID 2 */
-	outb(W83C553F_PIC2_ICW4, 0x01); /* x86 mode */
-	outb(W83C553F_PIC2_OCW1, 0xff); /* disable all IRQ's */
-	outb(W83C553F_PIC2_ELC, 0xde);	/* all IRQ's edge sensitive */
-
-	outb(W83C553F_TMR1_CMOD, 0x74);
-
-	outb(W83C553F_PIC2_OCW1, 0x20);
-	outb(W83C553F_PIC1_OCW1, 0x20);
-
-	outb(W83C553F_PIC2_OCW1, 0x2b);
-	outb(W83C553F_PIC1_OCW1, 0x2b);
-}
-
-void initialise_dma(void)
-{
-	unsigned int channel;
-	unsigned int rvalue1, rvalue2;
-
-	/* perform a H/W reset of the devices */
-
-	outb(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
-	outw(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
-
-	/* initialise all channels to a sane state */
-
-	for (channel = 0; channel < 4; channel++) {
-		/*
-		 * dependent upon the channel, setup the specifics:
-		 *
-		 * demand
-		 * address-increment
-		 * autoinitialize-disable
-		 * verify-transfer
-		 */
-
-		switch (channel) {
-		case 0:
-			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
-			rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
-			break;
-	    	case 1:
-			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
-			rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
-			break;
-		case 2:
-			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
-			rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
-			break;
-		case 3:
-			rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
-			rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
-			break;
-		default:
-			rvalue1 = 0x00;
-			rvalue2 = 0x00;
-			break;
-		}
-
-		/* write to write mode registers */
-
-		outb(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
-		outw(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
-	}
-
-	/* enable all channels */
-
-	outb(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
-	outw(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
-	/*
-	 * initialize the global DMA configuration
-	 *
-	 * DACK# active low
-	 * DREQ active high
-	 * fixed priority
-	 * channel group enable
-	 */
-
-	outb(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
-	outw(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
-}
-
-static void w83c553_enable_resources(device_t dev)
-{
-	pci_dev_enable_resources(dev);
-	enable_childrens_resources(dev);
-}
-
-static void w83c553_read_resources(device_t dev)
-{
-	struct resource* res;
-
-	pci_dev_read_resources(dev);
-
-	res = new_resource(dev, 1);
-	res->base = 0x0UL;
-	res->size = 0x400UL;
-	res->limit = 0xffffUL;
-	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = 0xfec00000;
-	res->size = 0x00001000;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static struct device_operations w83c553_ops  = {
-        .read_resources   = w83c553_read_resources,
-        .set_resources    = pci_dev_set_resources,
-        .enable_resources = w83c553_enable_resources,
-        .init             = w83c553_init,
-        .scan_bus         = scan_static_bus,
-};
-
-static const struct pci_driver w83c553f_pci_driver __pci_driver = {
-	/* w83c553f */
-	.ops = &w83c553_ops,
-	.device = PCI_DEVICE_ID_WINBOND_83C553,
-	.vendor = PCI_VENDOR_ID_WINBOND,
-};
diff --git a/src/southbridge/winbond/w83c553/w83c553f.h b/src/southbridge/winbond/w83c553/w83c553f.h
deleted file mode 100644
index 775b12453f..0000000000
--- a/src/southbridge/winbond/w83c553/w83c553f.h
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _W83C553_H
-#define _W83C553_H
-
- /* winbond access routines and defines*/
-
-/* from the winbond data sheet -
- The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
- Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
-*/
-
-/*ISA bridge configuration space*/
-
-#define W83C553F_VID		0x10AD
-#define W83C553F_DID		0x0565
-#define W83C553F_IDE		0x0105
-
-/* Function 0 registers */
-#define W83C553F_PCICONTR	0x40  /*pci control reg*/
-#define W83C553F_SGBAR		0x41  /*scatter/gather base address reg*/
-#define W83C553F_LBCR		0x42  /*Line Buffer Control reg*/
-#define W83C553F_IDEIRCR	0x43  /*IDE Interrupt Routing Control  Reg*/
-#define W83C553F_PCIIRCR	0x44  /*PCI Interrupt Routing Control Reg*/
-#define W83C553F_BTBAR		0x46  /*BIOS Timer Base Address Register*/
-#define W83C553F_IPADCR		0x48  /*ISA to PCI Address Decoder Control Register*/
-#define W83C553F_IRADCR		0x49  /*ISA ROM Address Decoder Control Register*/
-#define W83C553F_IPMHSAR	0x4a  /*ISA to PCI Memory Hole STart Address Register*/
-#define W83C553F_IPMHSR		0x4b  /*ISA to PCI Memory Hols Size Register*/
-#define W83C553F_CDR			0x4c  /*Clock Divisor Register*/
-#define W83C553F_CSCR		0x4d  /*Chip Select Control Register*/
-#define W83C553F_ATSCR		0x4e  /*AT System Control register*/
-#define W83C553F_ATBCR		0x4f  /*AT Bus ControL Register*/
-#define W83C553F_IRQBEE0R	0x60  /*IRQ Break Event Enable 0 Register*/
-#define W83C553F_IRQBEE1R	0x61  /*IRQ Break Event Enable 1 Register*/
-#define W83C553F_ABEER		0x62  /*Additional Break Event Enable Register*/
-#define W83C553F_DMABEER	0x63  /*DMA Break Event Enable Register*/
-
-/* Function 1 registers */
-#define W83C553F_PIR		0x09  /*Programming Interface Register*/
-#define W83C553F_IDECSR		0x40  /*IDE Control/Status Register*/
-
-/* register bit definitions */
-#define W83C553F_IPADCR_MBE512		0x1
-#define W83C553F_IPADCR_MBE640		0x2
-#define W83C553F_IPADCR_IPATOM4		0x10
-#define W83C553F_IPADCR_IPATOM5		0x20
-#define W83C553F_IPADCR_IPATOM6		0x40
-#define W83C553F_IPADCR_IPATOM7		0x80
-
-#define W83C553F_CSCR_UBIOSCSE		0x10
-#define W83C553F_CSCR_BIOSWP		0x20
-
-#define W83C553F_IDECSR_P0EN		0x01
-#define W83C553F_IDECSR_P0F16		0x02
-#define W83C553F_IDECSR_P1EN		0x10
-#define W83C553F_IDECSR_P1F16		0x20
-#define W83C553F_IDECSR_LEGIRQ		0x800
-
-#define W83C553F_ATSCR_ISARE		0x40
-#define W83C553F_ATSCR_FERRE		0x10
-#define W83C553F_ATSCR_P92E		0x04
-#define W83C553F_ATSCR_KRCEE		0x02
-#define W83C553F_ATSCR_KGA20EE		0x01
-
-#define W83C553F_PIR_BM			0x80
-#define W83C553F_PIR_P1PROG		0x08
-#define W83C553F_PIR_P1NL		0x04
-#define W83C553F_PIR_P0PROG		0x02
-#define W83C553F_PIR_P0NL		0x01
-
-/*
- * Interrupt controller
- */
-#define W83C553F_PIC1_ICW1	CONFIG_ISA_IO + 0x20
-#define W83C553F_PIC1_ICW2	CONFIG_ISA_IO + 0x21
-#define W83C553F_PIC1_ICW3	CONFIG_ISA_IO + 0x21
-#define W83C553F_PIC1_ICW4	CONFIG_ISA_IO + 0x21
-#define W83C553F_PIC1_OCW1	CONFIG_ISA_IO + 0x21
-#define W83C553F_PIC1_OCW2	CONFIG_ISA_IO + 0x20
-#define W83C553F_PIC1_OCW3	CONFIG_ISA_IO + 0x20
-#define W83C553F_PIC1_ELC	CONFIG_ISA_IO + 0x4D0
-#define W83C553F_PIC2_ICW1	CONFIG_ISA_IO + 0xA0
-#define W83C553F_PIC2_ICW2	CONFIG_ISA_IO + 0xA1
-#define W83C553F_PIC2_ICW3	CONFIG_ISA_IO + 0xA1
-#define W83C553F_PIC2_ICW4	CONFIG_ISA_IO + 0xA1
-#define W83C553F_PIC2_OCW1	CONFIG_ISA_IO + 0xA1
-#define W83C553F_PIC2_OCW2	CONFIG_ISA_IO + 0xA0
-#define W83C553F_PIC2_OCW3	CONFIG_ISA_IO + 0xA0
-#define W83C553F_PIC2_ELC	CONFIG_ISA_IO + 0x4D1
-
-#define W83C553F_TMR1_CMOD	CONFIG_ISA_IO + 0x43
-
-/*
- * DMA controller
- */
-#define W83C553F_DMA1	CONFIG_ISA_IO + 0x000	/* channel 0 - 3 */
-#define W83C553F_DMA2	CONFIG_ISA_IO + 0x0C0	/* channel 4 - 7 */
-
-/* command/status register bit definitions */
-
-#define W83C553F_CS_COM_DACKAL	(1<<7)	/* DACK# assert level */
-#define W83C553F_CS_COM_DREQSAL	(1<<6)	/* DREQ sense assert level */
-#define W83C553F_CS_COM_GAP	(1<<4)	/* group arbitration priority */
-#define W83C553F_CS_COM_CGE	(1<<2)	/* channel group enable */
-
-#define W83C553F_CS_STAT_CH0REQ	(1<<4)	/* channel 0 (4) DREQ status */
-#define W83C553F_CS_STAT_CH1REQ	(1<<5)	/* channel 1 (5) DREQ status */
-#define W83C553F_CS_STAT_CH2REQ	(1<<6)	/* channel 2 (6) DREQ status */
-#define W83C553F_CS_STAT_CH3REQ	(1<<7)	/* channel 3 (7) DREQ status */
-
-#define W83C553F_CS_STAT_CH0TC	(1<<0)	/* channel 0 (4) TC status */
-#define W83C553F_CS_STAT_CH1TC	(1<<1)	/* channel 1 (5) TC status */
-#define W83C553F_CS_STAT_CH2TC	(1<<2)	/* channel 2 (6) TC status */
-#define W83C553F_CS_STAT_CH3TC	(1<<3)	/* channel 3 (7) TC status */
-
-/* mode register bit definitions */
-
-#define W83C553F_MODE_TM_DEMAND	(0<<6)	/* transfer mode - demand */
-#define W83C553F_MODE_TM_SINGLE	(1<<6)	/* transfer mode - single */
-#define W83C553F_MODE_TM_BLOCK	(2<<6)	/* transfer mode - block */
-#define W83C553F_MODE_TM_CASCADE	(3<<6)	/* transfer mode - cascade */
-#define W83C553F_MODE_ADDRDEC	(1<<5)	/* address increment/decrement select */
-#define W83C553F_MODE_AUTOINIT	(1<<4)	/* autoinitialize enable */
-#define W83C553F_MODE_TT_VERIFY	(0<<2)	/* transfer type - verify */
-#define W83C553F_MODE_TT_WRITE	(1<<2)	/* transfer type - write */
-#define W83C553F_MODE_TT_READ	(2<<2)	/* transfer type - read */
-#define W83C553F_MODE_TT_ILLEGAL	(3<<2)	/* transfer type - illegal */
-#define W83C553F_MODE_CH0SEL	(0<<0)	/* channel 0 (4) select */
-#define W83C553F_MODE_CH1SEL	(1<<0)	/* channel 1 (5) select */
-#define W83C553F_MODE_CH2SEL	(2<<0)	/* channel 2 (6) select */
-#define W83C553F_MODE_CH3SEL	(3<<0)	/* channel 3 (7) select */
-
-/* request register bit definitions */
-
-#define W83C553F_REQ_CHSERREQ	(1<<2)	/* channel service request */
-#define W83C553F_REQ_CH0SEL	(0<<0)	/* channel 0 (4) select */
-#define W83C553F_REQ_CH1SEL	(1<<0)	/* channel 1 (5) select */
-#define W83C553F_REQ_CH2SEL	(2<<0)	/* channel 2 (6) select */
-#define W83C553F_REQ_CH3SEL	(3<<0)	/* channel 3 (7) select */
-
-/* write single mask bit register bit definitions */
-
-#define W83C553F_WSMB_CHMASKSEL	(1<<2)	/* channel mask select */
-#define W83C553F_WSMB_CH0SEL	(0<<0)	/* channel 0 (4) select */
-#define W83C553F_WSMB_CH1SEL	(1<<0)	/* channel 1 (5) select */
-#define W83C553F_WSMB_CH2SEL	(2<<0)	/* channel 2 (6) select */
-#define W83C553F_WSMB_CH3SEL	(3<<0)	/* channel 3 (7) select */
-
-/* read/write all mask bits register bit definitions */
-
-#define W83C553F_RWAMB_CH0MASK	(1<<0)	/* channel 0 (4) mask */
-#define W83C553F_RWAMB_CH1MASK	(1<<1)	/* channel 1 (5) mask */
-#define W83C553F_RWAMB_CH2MASK	(1<<2)	/* channel 2 (6) mask */
-#define W83C553F_RWAMB_CH3MASK	(1<<3)	/* channel 3 (7) mask */
-
-/* typedefs */
-
-#define W83C553F_DMA1_CS		0x8
-#define W83C553F_DMA1_WR		0x9
-#define W83C553F_DMA1_WSMB		0xA
-#define W83C553F_DMA1_WM		0xB
-#define W83C553F_DMA1_CBP		0xC
-#define W83C553F_DMA1_MC		0xD
-#define W83C553F_DMA1_CM		0xE
-#define W83C553F_DMA1_RWAMB		0xF
-
-#define W83C553F_DMA2_CS		0xD0
-#define W83C553F_DMA2_WR		0xD2
-#define W83C553F_DMA2_WSMB		0xD4
-#define W83C553F_DMA2_WM		0xD6
-#define W83C553F_DMA2_CBP		0xD8
-#define W83C553F_DMA2_MC		0xDA
-#define W83C553F_DMA2_CM		0xDC
-#define W83C553F_DMA2_RWAMB		0xDE
-
-#endif /* _W83C553_H */
diff --git a/src/southbridge/winbond/w83c553/w83c553f_ide.c b/src/southbridge/winbond/w83c553/w83c553f_ide.c
deleted file mode 100644
index d385cbfa26..0000000000
--- a/src/southbridge/winbond/w83c553/w83c553f_ide.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Andreas Heppel <aheppel@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Enable IDE controller of the W83C553F chip.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "w83c553f.h"
-
-#ifndef CONFIG_IDE_MAXBUS
-#define CONFIG_IDE_MAXBUS	2
-#endif
-#ifndef CONFIG_IDE_MAXDEVICE
-#define CONFIG_IDE_MAXDEVICE	(CONFIG_IDE_MAXBUS*2)
-#endif
-
-uint32_t ide_base[CONFIG_IDE_MAXBUS]; 
-
-static void 
-w83c553_ide_init(struct device *dev)
-{
-	unsigned char reg8;
-	unsigned short reg16;
-	unsigned int reg32;
-
-	printk_info("Configure W83C553F IDE (Function 1)\n");
-
-	/*
-	 * Enable native mode on IDE ports and set base address.
-	 */
-	reg8 = W83C553F_PIR_P1NL | W83C553F_PIR_P0NL;
-	pci_write_config8(dev, W83C553F_PIR, reg8);
-	pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0xffffffff);
-	reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-	pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0x1f0);
-	reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-	pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0xffffffff);
-	reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
-	pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x3f6);
-	reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
-	pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xffffffff);
-	reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
-	pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0x170);
-	reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
-	pci_write_config32(dev, PCI_BASE_ADDRESS_3, 0xffffffff);
-	reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_3);
-	pci_write_config32(dev, PCI_BASE_ADDRESS_3, 0x376);
-	reg32 = pci_read_config32(dev, PCI_BASE_ADDRESS_3);
-
-	/*
-	 * Set read-ahead duration to 0xff
-	 * Enable P0 and P1
-	 */
-	reg32 = 0x00ff0000 | W83C553F_IDECSR_P1EN | W83C553F_IDECSR_P0EN;
-	pci_write_config32(dev, W83C553F_IDECSR, reg32);
-
-	ide_base[0] = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-	printk_debug("ide bus offset = 0x%x\n", ide_base[0]);
-	ide_base[0] &= ~1;
-#if CONFIG_IDE_MAXBUS > 1
-	ide_base[1] = pci_read_config32(dev, PCI_BASE_ADDRESS_2);
-	ide_base[1] &= ~1;
-#endif
-
-	/*
-	 * Enable function 1, IDE -> busmastering and IO space access
-	 */
-	reg16 = pci_read_config16(dev, PCI_COMMAND);
-	reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
-	pci_write_config16(dev, PCI_COMMAND, reg16);
-
-	printk_info("IDE configuration complete\n");
-}
-
-static struct device_operations w83c553_ide_ops  = {
-        .read_resources   = pci_dev_read_resources,
-        .set_resources    = pci_dev_set_resources,
-        .enable_resources = pci_dev_enable_resources,
-        .init             = w83c553_ide_init,
-        .scan_bus         = 0,
-};
-
-static const struct pci_driver w83c553f_ide_pci_driver __pci_driver = {
-	/* w83c553f_ide */
-	.ops = &w83c553_ide_ops,
-	.device = PCI_DEVICE_ID_WINBOND_82C105,
-	.vendor = PCI_VENDOR_ID_WINBOND,
-};