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authorRudolf Marek <r.marek@assembler.cz>2008-03-15 00:26:50 +0000
committerRudolf Marek <r.marek@assembler.cz>2008-03-15 00:26:50 +0000
commit5671787b9e36ca80b39dcbbfb0307e3c697c8e20 (patch)
treef6eeff657df63286badb6fed864d0c4e793f5ed2 /src/southbridge/via
parentdd52e17448b2a8b49c1add655aa3deb3adebbcbc (diff)
Following patch extends the ROM decoding to last 1MB, allowing to use larger
flashes such as SST49LF080A: 1024K x8 (8 Mbit) Tested on my system, the flash is found and if I use coreboot in second half it works too. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via')
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_early_smbus.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
index 9116e46dbd..5e62f39e4d 100644
--- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
+++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
@@ -212,3 +212,18 @@ void smbus_fixup(const struct mem_controller *ctrl)
else
PRINT_DEBUG("Done\r\n");
}
+
+void enable_rom_decode(void)
+{
+ device_t dev;
+
+ /* Bus Control and Power Management */
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+
+ if (dev == PCI_DEV_INVALID)
+ die("SB not found\r\n");
+
+ /* ROM decode last 1MB FFC00000 - FFFFFFFF */
+ pci_write_config8(dev, 0x41, 0x7f);
+}