diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-04-23 12:31:01 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-04-28 05:45:37 +0200 |
| commit | 0c85b7f4d7180c9307fd95bb887791d4231397a5 (patch) | |
| tree | 0caa24e1c6b2d70b8d184337e9cc891b58fd10ea /src/southbridge/via | |
| parent | e976bd44692d2adb320a1256f1b6bfaa6469108a (diff) | |
soc/intel/apollolake: Add cache for BIOS ROM
Enable caching of BIOS region with variable MTRR. This is most
useful if enabled early such as in bootblock.
Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14480
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/via')
0 files changed, 0 insertions, 0 deletions