diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2018-07-13 09:52:04 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-09-21 14:14:10 +0000 |
| commit | 83e73249693f3aabc1d47212ab45c3acd792c9ee (patch) | |
| tree | 5b9e972fe9e68496be04424ff7ce3b7efba13006 /src/southbridge/via | |
| parent | dc0352835525598e0c72d6fbcfba428113847e59 (diff) | |
soc/intel/braswell/ramstage.c: Add SoC stepping D-1 support
No support for SoC D-1 stepping is available.
According to Intel doc #332095-015 stepping C-0 has revision
id 0x21 and D-1 revision ID 0x35.
Also correct the RID_C_STEPPING_START value for C-0.
BUG=none
TEST=Built, Intel Cherry Hill Rev F.
Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27471
Reviewed-by: Wim Vervoorn
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/via')
0 files changed, 0 insertions, 0 deletions