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authorRudolf Marek <r.marek@assembler.cz>2009-04-13 18:00:09 +0000
committerRudolf Marek <r.marek@assembler.cz>2009-04-13 18:00:09 +0000
commit497c8effceb9510ca89561a8fcc87cbc0acb8b08 (patch)
treeaaaeaeda460a8f7c351488a424678bcefc211d9f /src/southbridge/via
parenta572f83e7198eff99728335e697e9a0ef1e53a0c (diff)
Following patch adds support for resume on VT8237 based motherboards. The NB
part of this patch adds support for resume well NVRAM. In which DQS values are stored. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via')
-rw-r--r--src/southbridge/via/k8t890/k8t890.h4
-rw-r--r--src/southbridge/via/k8t890/k8t890_early_car.c64
-rw-r--r--src/southbridge/via/k8t890/k8t890_host_ctrl.c21
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_early_smbus.c31
-rw-r--r--src/southbridge/via/vt8237r/vt8237r_lpc.c23
5 files changed, 128 insertions, 15 deletions
diff --git a/src/southbridge/via/k8t890/k8t890.h b/src/southbridge/via/k8t890/k8t890.h
index 9159b53d5c..59d47ee52c 100644
--- a/src/southbridge/via/k8t890/k8t890.h
+++ b/src/southbridge/via/k8t890/k8t890.h
@@ -29,6 +29,9 @@
*/
#define K8T890_APIC_BASE 0xfecc0000
+/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
+#define K8T890_NVRAM_IO_BASE 0xf00
+
#define K8T890_MMCONFIG_MBAR 0x61
#define K8T890_MULTIPLE_FN_EN 0x4f
@@ -36,6 +39,7 @@
#define K8M890_FBSIZEMB 64
#include <device/device.h>
+
extern void writeback(struct device *dev, u16 where, u8 what);
extern void dump_south(device_t dev);
diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c
index a14e2a2715..4f53486ed0 100644
--- a/src/southbridge/via/k8t890/k8t890_early_car.c
+++ b/src/southbridge/via/k8t890/k8t890_early_car.c
@@ -23,6 +23,15 @@
*/
#include <stdlib.h>
+//include "k8t890.h"
+#warning hack the right header here
+
+/* The 256 bytes of NVRAM for S3 storage, 256B aligned */
+#define K8T890_NVRAM_IO_BASE 0xf00
+#define K8T890_MULTIPLE_FN_EN 0x4f
+/* we provide S3 NVRAM to system */
+#define S3_NVRAM_EARLY 1
+
/* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
static ldtreg[3] = {0x86, 0xa6, 0xc6};
@@ -33,10 +42,22 @@ static ldtreg[3] = {0x86, 0xa6, 0xc6};
u8 k8t890_early_setup_ht(void)
{
- u8 awidth, afreq, cldtfreq;
+ u8 awidth, afreq, cldtfreq, reg;
u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width;
u16 vldtcaps;
+ /* hack, enable NVRAM in chipset */
+ pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01);
+
+ /*
+ * NVRAM I/O base at K8T890_NVRAM_IO_BASE
+ */
+
+ pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+ reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1);
+ reg |= 0x1;
+ pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg);
+
/* check if connected non coherent, initcomplete (find the SB on K8 side) */
if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) {
ldtnr = 0;
@@ -90,3 +111,44 @@ u8 k8t890_early_setup_ht(void)
return 1;
}
+
+int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
+
+ printk_debug("Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
+ switch (size) {
+ case 1:
+ outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos);
+ nvram_pos +=1;
+ break;
+ case 2:
+ outw((dword & 0xffff), K8T890_NVRAM_IO_BASE+nvram_pos);
+ nvram_pos +=2;
+ break;
+ default:
+ outl(dword, K8T890_NVRAM_IO_BASE+nvram_pos);
+ nvram_pos +=4;
+ break;
+ }
+ return nvram_pos;
+}
+
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+ switch (size) {
+ case 1:
+ *old_dword &= ~0xff;
+ *old_dword |= inb(K8T890_NVRAM_IO_BASE+nvram_pos);
+ nvram_pos +=1;
+ break;
+ case 2:
+ *old_dword &= ~0xffff;
+ *old_dword |= inw(K8T890_NVRAM_IO_BASE+nvram_pos);
+ nvram_pos +=2;
+ break;
+ default:
+ *old_dword = inl(K8T890_NVRAM_IO_BASE+nvram_pos);
+ nvram_pos +=4;
+ break;
+ }
+ printk_debug("Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size);
+ return nvram_pos;
+}
diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
index 71f863bdc8..9ed89eba12 100644
--- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
@@ -37,14 +37,14 @@ static void host_ctrl_enable_k8t890(struct device *dev)
*/
pci_write_config8(dev, 0xa0, 0x13);
- /* Disable NVRAM and enable non-posted PCI writes. */
- pci_write_config8(dev, 0xa1, 0x8e);
-
/*
- * NVRAM I/O base 0xe00-0xeff, but it is disabled.
+ * NVRAM I/O base at K8T890_NVRAM_IO_BASE
* Some bits are set and reserved.
*/
- pci_write_config8(dev, 0xa2, 0x0e);
+ pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+
+ /* enable NB NVRAM and enable non-posted PCI writes. */
+ pci_write_config8(dev, 0xa1, 0x8f);
/* Arbitration control, some bits are reserved. */
pci_write_config8(dev, 0xa5, 0x3c);
@@ -95,14 +95,15 @@ static void host_ctrl_enable_k8m890(struct device *dev) {
*/
pci_write_config8(dev, 0xa0, 0x13);
- /* Disable NVRAM and enable non-posted PCI writes. */
- pci_write_config8(dev, 0xa1, 0x8e);
-
/*
- * NVRAM I/O base 0xe00-0xeff, but it is disabled.
+ * NVRAM I/O base at K8T890_NVRAM_IO_BASE
*/
- pci_write_config8(dev, 0xa2, 0x0e);
+ pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+
+ /* Enable NVRAM and enable non-posted PCI writes. */
+ pci_write_config8(dev, 0xa1, 0x8f);
+
/* Arbitration control */
pci_write_config8(dev, 0xa5, 0x3c);
diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
index 49f3d90020..17b32d529f 100644
--- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
+++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
@@ -294,6 +294,37 @@ void enable_rom_decode(void)
pci_write_config8(dev, 0x41, 0x7f);
}
+#define ACPI_IS_WAKEUP_EARLY 1
+
+int acpi_is_wakeup_early(void) {
+ device_t dev;
+ u16 tmp;
+
+ print_debug("IN TEST WAKEUP\n");
+
+ /* Power management controller */
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ if (dev == PCI_DEV_INVALID) {
+ /* Power management controller */
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
+ if (dev == PCI_DEV_INVALID)
+ die("Power management controller not found\r\n");
+ }
+
+ /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
+ pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
+
+ /* Enable ACPI accessm RTC signal gated with PSON. */
+ pci_write_config8(dev, 0x81, 0x84);
+
+ tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
+
+ print_debug_hex8(tmp);
+ return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
+}
+
#if defined(__GNUC__)
void vt8237_early_spi_init(void)
{
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index 4fbc29575a..d33dc48231 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -149,8 +149,13 @@ static void pci_routing_fixup(struct device *dev)
* Set up the power management capabilities directly into ACPI mode.
* This avoids having to handle any System Management Interrupts (SMIs).
*/
+
+extern u8 acpi_slp_type;
+
+
static void setup_pm(device_t dev)
{
+ u16 tmp;
/* Debounce LID and PWRBTN# Inputs for 16ms. */
pci_write_config8(dev, 0x80, 0x20);
@@ -171,10 +176,10 @@ static void setup_pm(device_t dev)
/*
* 7 = SMBus clock from RTC 32.768KHz
- * 5 = Internal PLL reset from susp
- * 2 = GPO2 is GPIO
+ * 5 = Internal PLL reset from susp disabled
+ * 2 = GPO2 is SUSA#
*/
- pci_write_config8(dev, 0x94, 0xa4);
+ pci_write_config8(dev, 0x94, 0xa0);
/*
* 7 = stp to sust delay 1msec
@@ -219,7 +224,17 @@ static void setup_pm(device_t dev)
outb(0x0, VT8237R_ACPI_IO_BASE + 0x42);
/* SCI is generated for RTC/pwrBtn/slpBtn. */
- outw(0x001, VT8237R_ACPI_IO_BASE + 0x04);
+ tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
+ acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
+ printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
+ /* clear sleep */
+ tmp &= ~(7 << 10);
+ tmp |= 1;
+ outw(tmp, VT8237R_ACPI_IO_BASE + 0x04);
+
+
+
+
}
static void vt8237r_init(struct device *dev)