Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

21 files changed, 172 insertions, 172 deletions

diff --git a/src/southbridge/via/k8t890/k8t890_bridge.c b/src/southbridge/via/k8t890/k8t890_bridge.c
index e30cf60b4d..3e1e81730d 100644
--- a/src/southbridge/via/k8t890/k8t890_bridge.c
+++ b/src/southbridge/via/k8t890/k8t890_bridge.c
@@ -32,14 +32,14 @@ static void bridge_enable(struct device *dev)
 	writeback(dev, 0x40, 0x91);
 	writeback(dev, 0x41, 0x40);
 	writeback(dev, 0x43, 0x44);
-	writeback(dev, 0x44, 0x31); 	/* K8M890 should have 0x35 datasheet 
-					 * says it is reserved 
+	writeback(dev, 0x44, 0x31); 	/* K8M890 should have 0x35 datasheet
+					 * says it is reserved
 					 */
 	writeback(dev, 0x45, 0x3a);
 	writeback(dev, 0x46, 0x88);	/* PCI ID lo */
 	writeback(dev, 0x47, 0xb1);	/* PCI ID hi */
 
-	/* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP 
+	/* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP
 	 * (Forward VGA compatible memory and I/O cycles )
 	 */
 
diff --git a/src/southbridge/via/k8t890/k8t890_ctrl.c b/src/southbridge/via/k8t890/k8t890_ctrl.c
index ad17fe624d..48aa739257 100644
--- a/src/southbridge/via/k8t890/k8t890_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_ctrl.c
@@ -23,7 +23,7 @@
 #include <device/pci_ids.h>
 #include <console/console.h>
 
-/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate 
+/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
  * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
  */
 
diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c
index 0505a6ff5a..037f5a75eb 100644
--- a/src/southbridge/via/k8t890/k8t890_early_car.c
+++ b/src/southbridge/via/k8t890/k8t890_early_car.c
@@ -38,7 +38,7 @@ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
 
 /* This functions sets KT890 link frequency and width to same values as
  * it has been setup on K8 side, by AMD NB init.
- */ 
+ */
 
 u8 k8t890_early_setup_ht(void)
 {
@@ -115,7 +115,7 @@ u8 k8t890_early_setup_ht(void)
 
 static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
-	
+
 	printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
 	switch (size) {
 	case 1:
diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
index 38f69680fe..a1c42b7d59 100644
--- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c
+++ b/src/southbridge/via/k8t890/k8t890_host_ctrl.c
@@ -52,7 +52,7 @@ static void host_ctrl_enable_k8t890(struct device *dev)
 	pci_write_config8(dev, 0xa6, 0x80);
 
 	/* this will be possibly removed, when I figure out
-	 * if the ROM SIP is good, second reason is that the 
+	 * if the ROM SIP is good, second reason is that the
 	 * unknown bits are AGP related, which are dummy on K8T890
 	 */
 
diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc
index 9642aa4d5c..aaaa76694d 100644
--- a/src/southbridge/via/k8t890/romstrap.inc
+++ b/src/southbridge/via/k8t890/romstrap.inc
@@ -48,7 +48,7 @@ tblpointer:
 .long 0x0
 .long 0x0
 .long 0x0
-.long 0x0 
+.long 0x0
 
 /*
  * The pointer to above table should be at 0xffffd,
diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c
index 43238ec050..85f007a097 100644
--- a/src/southbridge/via/vt8231/vt8231.c
+++ b/src/southbridge/via/vt8231/vt8231.c
@@ -18,7 +18,7 @@ static void keyboard_on(void)
 
 	if (lpc_dev) {
 		regval = pci_read_config8(lpc_dev, 0x51);
-		regval |= 0x0f; 
+		regval |= 0x0f;
 		pci_write_config8(lpc_dev, 0x51, regval);
 	}
 	pc_keyboard_init(0);
@@ -27,9 +27,9 @@ static void keyboard_on(void)
 static void com_port_on(void)
 {
 #if 0
-	// enable com1 and com2. 
+	// enable com1 and com2.
 	enables = pci_read_config8(dev, 0x6e);
-	
+
 	/* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
 	 * is enable com port a as com1 kevinh/Ispiri - Old code
 	 * thought 0x01 would make it com1, that was wrong enables =
diff --git a/src/southbridge/via/vt8231/vt8231_acpi.c b/src/southbridge/via/vt8231/vt8231_acpi.c
index 6cbf4c591f..647910aef6 100644
--- a/src/southbridge/via/vt8231/vt8231_acpi.c
+++ b/src/southbridge/via/vt8231/vt8231_acpi.c
@@ -10,20 +10,20 @@ static void acpi_init(struct device *dev)
 
 	// Set ACPI base address to IO 0x4000
 	pci_write_config32(dev, 0x48, 0x4001);
-	
+
 	// Enable ACPI access (and setup like award)
 	pci_write_config8(dev, 0x41, 0x84);
-	
+
 	// Set hardware monitor base address to IO 0x6000
 	pci_write_config32(dev, 0x70, 0x6001);
-	
+
 	// Enable hardware monitor (and setup like award)
 	pci_write_config8(dev, 0x74, 0x01);
-	
+
 	// set IO base address to 0x5000
 	pci_write_config32(dev, 0x90, 0x5001);
-	
-	// Enable SMBus 
+
+	// Enable SMBus
 	pci_write_config8(dev, 0xd2, 0x01);
 }
 
diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/vt8231_early_serial.c
index 5b38b8e521..af5a7729ee 100644
--- a/src/southbridge/via/vt8231/vt8231_early_serial.c
+++ b/src/southbridge/via/vt8231/vt8231_early_serial.c
@@ -8,18 +8,18 @@
 #define SIO_BASE 0x3f0
 #define SIO_DATA  SIO_BASE+1
 
-static void vt8231_writesuper(uint8_t reg, uint8_t val) 
+static void vt8231_writesuper(uint8_t reg, uint8_t val)
 {
 	outb(reg, SIO_BASE);
 	outb(val, SIO_DATA);
 }
 
-static void vt8231_writesiobyte(uint16_t reg, uint8_t val) 
+static void vt8231_writesiobyte(uint16_t reg, uint8_t val)
 {
 	outb(val, reg);
 }
 
-static void vt8231_writesioword(uint16_t reg, uint16_t val) 
+static void vt8231_writesioword(uint16_t reg, uint16_t val)
 {
 	outw(val, reg);
 }
@@ -29,26 +29,26 @@ static void vt8231_writesioword(uint16_t reg, uint16_t val)
    mainboard
  */
 
-static void enable_vt8231_serial(void) 
+static void enable_vt8231_serial(void)
 {
 	uint8_t c;
 	device_t dev;
 	outb(6, 0x80);
 	dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
-	
+
 	if (dev == PCI_DEV_INVALID) {
 		outb(7, 0x80);
 		die("Serial controller not found\n");
 	}
-	
-	/* first, you have to enable the superio and superio config. 
+
+	/* first, you have to enable the superio and superio config.
 	   put a 6 reg 80
 	*/
 	c = pci_read_config8(dev, 0x50);
 	c |= 6;
 	pci_write_config8(dev, 0x50, c);
 	outb(2, 0x80);
-	// now go ahead and set up com1. 
+	// now go ahead and set up com1.
 	// set address
 	vt8231_writesuper(0xf4, 0xfe);
 	// enable serial out
diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c
index 40ef656c00..8ba72a387b 100644
--- a/src/southbridge/via/vt8231/vt8231_early_smbus.c
+++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c
@@ -35,7 +35,7 @@ static void enable_smbus(void)
 	// set IO base address to SMBUS_IO_BASE
 	pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
 
-	// Enable SMBus 
+	// Enable SMBus
 	c = pci_read_config8(dev, 0xd2);
 	c |= 5;
 	pci_write_config8(dev, 0xd2, c);
@@ -244,7 +244,7 @@ static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex)
 
 }
 #endif
-/* for reference, here is the fancier version which we will use at some 
+/* for reference, here is the fancier version which we will use at some
  * point
  */
 # if 0
diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c
index c1df5ef5cd..46479c4af3 100644
--- a/src/southbridge/via/vt8231/vt8231_ide.c
+++ b/src/southbridge/via/vt8231/vt8231_ide.c
@@ -18,7 +18,7 @@ static void ide_init(struct device *dev)
 		* or it is possibly a timing issue. Ben Hewson 29 Apr 2007.
 		*/
 
-		/*		
+		/*
 		printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__);
 		enables = pci_read_config8(dev, 0x42);
 		printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
@@ -28,73 +28,73 @@ static void ide_init(struct device *dev)
 		printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables);
 		*/
 	}
-	
+
 	enables = pci_read_config8(dev, 0x40);
 	printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
 	enables |= 3;
 	pci_write_config8(dev, 0x40, enables);
 	enables = pci_read_config8(dev, 0x40);
 	printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
-	
+
 	// Enable prefetch buffers
 	enables = pci_read_config8(dev, 0x41);
 	enables |= 0xf0;
 	pci_write_config8(dev, 0x41, enables);
-	
+
 	// Lower thresholds (cause award does it)
 	enables = pci_read_config8(dev, 0x43);
 	enables &= ~0x0f;
 	enables |=  0x05;
 	pci_write_config8(dev, 0x43, enables);
-	
+
 	// PIO read prefetch counter (cause award does it)
 	pci_write_config8(dev, 0x44, 0x18);
-	
+
 	// Use memory read multiple
 	pci_write_config8(dev, 0x45, 0x1c);
-	
-	// address decoding. 
+
+	// address decoding.
 	// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
-	// kevinh@ispiri.com - the standard linux drivers seem ass slow when 
+	// kevinh@ispiri.com - the standard linux drivers seem ass slow when
 	// used in native mode - I've changed back to classic
 	enables = pci_read_config8(dev, 0x9);
 	printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
-	// by the book, set the low-order nibble to 0xa. 
+	// by the book, set the low-order nibble to 0xa.
 	if (conf->enable_native_ide) {
 		enables &= ~0xf;
-		// cf/cg silicon needs an 'f' here. 
+		// cf/cg silicon needs an 'f' here.
 		enables |= 0xf;
 	} else {
 		enables &= ~0x5;
 	}
-	
+
 	pci_write_config8(dev, 0x9, enables);
 	enables = pci_read_config8(dev, 0x9);
 	printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
-	
-	// standard bios sets master bit. 
+
+	// standard bios sets master bit.
 	enables = pci_read_config8(dev, 0x4);
 	printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
 	enables |= 7;
-	
+
 	// No need for stepping - kevinh@ispiri.com
 	enables &= ~0x80;
-	
+
 	pci_write_config8(dev, 0x4, enables);
 	enables = pci_read_config8(dev, 0x4);
 	printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
-	
+
 	if (!conf->enable_native_ide) {
 		// Use compatability mode - per award bios
 		pci_write_config32(dev, 0x10, 0x0);
 		pci_write_config32(dev, 0x14, 0x0);
 		pci_write_config32(dev, 0x18, 0x0);
 		pci_write_config32(dev, 0x1c, 0x0);
-		
+
 		// Force interrupts to use compat mode - just like Award bios
 		pci_write_config8(dev, 0x3d, 00);
 		pci_write_config8(dev, 0x3c, 0xff);
-	}	
+	}
 }
 
 static struct device_operations ide_ops = {
diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c
index 6c517ff492..c874528dec 100644
--- a/src/southbridge/via/vt8231/vt8231_lpc.c
+++ b/src/southbridge/via/vt8231/vt8231_lpc.c
@@ -25,7 +25,7 @@ static void pci_routing_fixup(struct device *dev)
 	printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
 	if (dev) {
 		/* initialize PCI interupts - these assignments depend
-		   on the PCB routing of PINTA-D 
+		   on the PCB routing of PINTA-D
 
 		   PINTA = IRQ11
 		   PINTB = IRQ5
@@ -61,60 +61,60 @@ static void vt8231_init(struct device *dev)
 	enables = pci_read_config8(dev, 0x6C);
 	enables |= 0x80;
 	pci_write_config8(dev, 0x6C, enables);
-	
+
 	// Map 4MB of FLASH into the address space
 	pci_write_config8(dev, 0x41, 0x7f);
-	
+
 	// Set bit 6 of 0x40, because Award does it (IO recovery time)
-	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI 
+	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
 	// interrupts can be properly marked as level triggered.
 	enables = pci_read_config8(dev, 0x40);
 	pci_write_config8(dev, 0x40, enables);
-	
+
 	// Set 0x42 to 0xf0 to match Award bios
 	enables = pci_read_config8(dev, 0x42);
 	enables |= 0xf0;
 	pci_write_config8(dev, 0x42, enables);
-	
+
 	// Set bit 3 of 0x4a, to match award (dummy pci request)
 	enables = pci_read_config8(dev, 0x4a);
 	enables |= 0x08;
 	pci_write_config8(dev, 0x4a, enables);
-	
+
 	// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
 	enables = pci_read_config8(dev, 0x4f);
 	enables |= 0x08;
 	pci_write_config8(dev, 0x4f, enables);
-	
+
 	// Set 0x58 to 0x03 to match Award
 	pci_write_config8(dev, 0x58, 0x03);
-	
+
 	// enable the ethernet/RTC
 	if (dev) {
 		enables = pci_read_config8(dev, 0x51);
-		enables |= 0x18; 
+		enables |= 0x18;
 		pci_write_config8(dev, 0x51, enables);
 	}
 
 	// enable IDE, since Linux won't do it.
 	// First do some more things to devfn (17,0)
-	// note: this should already be cleared, according to the book. 
+	// note: this should already be cleared, according to the book.
 	enables = pci_read_config8(dev, 0x50);
 	printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables);
 	enables &= ~8; // need manifest constant here!
 	printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables);
 	pci_write_config8(dev, 0x50, enables);
-	
+
 	// set default interrupt values (IDE)
 	enables = pci_read_config8(dev, 0x4c);
 	printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf);
-	// clear out whatever was there. 
+	// clear out whatever was there.
 	enables &= ~0xf;
 	enables |= 4;
 	printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables);
 	pci_write_config8(dev, 0x4c, enables);
-	
-	// set up the serial port interrupts. 
+
+	// set up the serial port interrupts.
 	// com2 to 3, com1 to 4
 	pci_write_config8(dev, 0x46, 0x04);
 	pci_write_config8(dev, 0x47, 0x03);
@@ -123,7 +123,7 @@ static void vt8231_init(struct device *dev)
 	/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
 	pci_write_config8(dev, 0x40, 0x54);
 	//ethernet_fixup();
-	
+
 	// Start the rtc
 	rtc_init(0);
 }
diff --git a/src/southbridge/via/vt8231/vt8231_nic.c b/src/southbridge/via/vt8231/vt8231_nic.c
index d4771f6816..5cd6cd8ca1 100644
--- a/src/southbridge/via/vt8231/vt8231_nic.c
+++ b/src/southbridge/via/vt8231/vt8231_nic.c
@@ -5,7 +5,7 @@
 #include <device/pci_ids.h>
 
 /*
- * Enable the ethernet device and turn off stepping (because it is integrated 
+ * Enable the ethernet device and turn off stepping (because it is integrated
  * inside the southbridge)
  */
 static void nic_init(struct device *dev)
diff --git a/src/southbridge/via/vt8231/vt8231_usb.c b/src/southbridge/via/vt8231/vt8231_usb.c
index 3dd0b4272b..e12a8db85a 100644
--- a/src/southbridge/via/vt8231/vt8231_usb.c
+++ b/src/southbridge/via/vt8231/vt8231_usb.c
@@ -9,7 +9,7 @@ static void usb_on(int enable)
 	device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
 	/* USB controller 2 */
 	device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
-	
+
 	/* enable USB1 */
 	if(dev2) {
 		if (enable) {
@@ -20,16 +20,16 @@ static void usb_on(int enable)
 			pci_write_config8(dev2, 0x04, 0x00);
 		}
 	}
-	
+
 	if(dev0) {
 		regval = pci_read_config8(dev0, 0x50);
-		if (enable) 
-			regval &= ~(0x10);    
+		if (enable)
+			regval &= ~(0x10);
 		else
-			regval |= 0x10;    	      
+			regval |= 0x10;
 		pci_write_config8(dev0, 0x50, regval);
 	}
-	
+
 	/* enable USB2 */
 	if(dev3) {
 		if (enable) {
@@ -40,13 +40,13 @@ static void usb_on(int enable)
 			pci_write_config8(dev3, 0x04, 0x00);
 		}
 	}
-	
+
 	if(dev0) {
 		regval = pci_read_config8(dev0, 0x50);
-		if (enable) 
-			regval &= ~(0x20);    
+		if (enable)
+			regval &= ~(0x20);
 		else
-			regval |= 0x20;    
+			regval |= 0x20;
 		pci_write_config8(dev0, 0x50, regval);
 	}
 }
diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c
index 747c2157f1..4fa2784661 100644
--- a/src/southbridge/via/vt8235/vt8235.c
+++ b/src/southbridge/via/vt8235/vt8235.c
@@ -12,7 +12,7 @@ static void keyboard_on(struct device *dev)
 	u8 regval;
 
 	regval = pci_read_config8(dev, 0x51);
-	regval |= 0x05; 
+	regval |= 0x05;
 	regval &= 0xfd;
 	pci_write_config8(dev, 0x51, regval);
 
@@ -23,7 +23,7 @@ static void keyboard_on(struct device *dev)
 void dump_south(device_t dev0)
 {
 	int i,j;
-	
+
 	for(i = 0; i < 256; i += 16) {
 		printk(BIOS_DEBUG, "0x%x: ", i);
 		for(j = 0; j < 16; j++) {
@@ -51,10 +51,10 @@ static void vt8235_enable(struct device *dev)
 	model = pci_read_config16(dev,0x2);
 
 	printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model);
-	
+
 	/* If this is not the southbridge itself just return.
 	 * This is necessary because USB devices are slot 10, whereas this
-	 * device is slot 11 therefore usb devices get called first during 
+	 * device is slot 11 therefore usb devices get called first during
 	 * the bus scan. We don't want to wait until we could do dev->init
 	 * because that's too late.
 	 */
@@ -69,13 +69,13 @@ static void vt8235_enable(struct device *dev)
 
 	/* enable RTC and ethernet */
 	regval = pci_read_config8(dev, 0x51);
-	regval |= 0x18; 
+	regval |= 0x18;
 	pci_write_config8(dev, 0x51, regval);
 
 	/* turn on keyboard */
 	keyboard_on(dev);
 
-	/* enable USB 1.1 & USB 2.0 - redundant really since we've 
+	/* enable USB 1.1 & USB 2.0 - redundant really since we've
 	 * already been there - see note above
 	 */
    	regval = pci_read_config8(dev, 0x50);
diff --git a/src/southbridge/via/vt8235/vt8235_early_serial.c b/src/southbridge/via/vt8235/vt8235_early_serial.c
index 7823172485..11f98fae39 100644
--- a/src/southbridge/via/vt8235/vt8235_early_serial.c
+++ b/src/southbridge/via/vt8235/vt8235_early_serial.c
@@ -8,25 +8,25 @@
 #define SIO_BASE 0x3f0
 #define SIO_DATA  SIO_BASE+1
 
-static void vt8235_writepnpaddr(uint8_t val) 
+static void vt8235_writepnpaddr(uint8_t val)
 {
 	outb(val, 0x2e);
 	outb(val, 0xeb);
 }
 
-static void vt8235_writepnpdata(uint8_t val) 
+static void vt8235_writepnpdata(uint8_t val)
 {
 	outb(val, 0x2f);
 	outb(val, 0xeb);
 }
 
 
-static void vt8235_writesiobyte(uint16_t reg, uint8_t val) 
+static void vt8235_writesiobyte(uint16_t reg, uint8_t val)
 {
 	outb(val, reg);
 }
 
-static void vt8235_writesioword(uint16_t reg, uint16_t val) 
+static void vt8235_writesioword(uint16_t reg, uint16_t val)
 {
 	outw(val, reg);
 }
@@ -36,12 +36,12 @@ static void vt8235_writesioword(uint16_t reg, uint16_t val)
    mainboard
  */
 
-static void enable_vt8235_serial(void) 
+static void enable_vt8235_serial(void)
 {
 	// turn on pnp
 	vt8235_writepnpaddr(0x87);
 	vt8235_writepnpaddr(0x87);
-	// now go ahead and set up com1. 
+	// now go ahead and set up com1.
 	// set address
 	vt8235_writepnpaddr(0x7);
 	vt8235_writepnpdata(0x2);
diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c
index db403eb5fb..1876461a3d 100644
--- a/src/southbridge/via/vt8235/vt8235_early_smbus.c
+++ b/src/southbridge/via/vt8235/vt8235_early_smbus.c
@@ -12,7 +12,7 @@
 #define SMBTRNSADD 0x9
 #define SMBSLVDATA 0xa
 #define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL  0xf 
+#define SMBUS_PIN_CTL  0xf
 
 /* Define register settings */
 #define HOST_RESET 0xff
@@ -34,17 +34,17 @@ static void enable_smbus(void)
 	/* Power management controller */
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 				PCI_DEVICE_ID_VIA_8235), 0);
-	
+
 	if (dev == PCI_DEV_INVALID) {
 		die("SMBUS controller not found\n");
-	}		
+	}
 
 	// set IO base address to SMBUS_IO_BASE
 	pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
-	
-	// Enable SMBus 
+
+	// Enable SMBus
 	pci_write_config8(dev, 0xd2, (0x4 << 1) | 1);
-	
+
 	/* make it work for I/O ...
 	 */
 	pci_write_config16(dev, 4, 1);
@@ -55,13 +55,13 @@ static void enable_smbus(void)
 	for(i = 0 ; i < 5000 ; i++)
 		outb(0x80,0x80);
 
-	/* 
+	/*
 	 * The VT1211 serial port needs 48 mhz clock, on power up it is getting
 	 *  only 24 mhz, there is some mysterious device on the smbus that can
 	 *  fix this...this code below does it.
 	 *  */
-	outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT); 
-	outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0); 
+	outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
+	outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
 	outb(0x83, SMBUS_IO_BASE+SMBHSTCMD);
 	outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD);
 	outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL);
@@ -92,7 +92,7 @@ static int smbus_wait_until_ready(void)
 			print_debug_hex8(c);
 			print_debug("\n");
 			c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-			/* nop */ 
+			/* nop */
 		}
 
 	} while(--loops);
@@ -105,13 +105,13 @@ void smbus_reset(void)
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
 	outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
-	
+
 	smbus_wait_until_ready();
 	print_debug("After reset status ");
 	print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
 	print_debug("\n");
 }
-  
+
 
 
 static int smbus_wait_until_done(void)
@@ -121,11 +121,11 @@ static int smbus_wait_until_done(void)
 	loops = SMBUS_TIMEOUT;
 	do {
 		smbus_delay();
-		
+
 		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 		if (byte & 1)
 			break;
-		
+
 	} while(--loops);
 	return loops?0:-1;
 }
@@ -156,46 +156,46 @@ static void smbus_print_error(unsigned char host_status_register)
 
 /* SMBus routines borrowed from VIA's Trident Driver */
 /* this works, so I am not going to touch it for now -- rgm */
-static unsigned char smbus_read_byte(unsigned char devAdr, 
-				unsigned char bIndex) 
+static unsigned char smbus_read_byte(unsigned char devAdr,
+				unsigned char bIndex)
 {
 	unsigned short i;
 	unsigned char  bData;
 	unsigned char  sts = 0;
-	
+
 	/* clear host status */
 	outb(0xff, SMBUS_IO_BASE);
-	
+
 	/* check SMBUS ready */
 	for ( i = 0; i < 0xFFFF; i++ )
 		if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
 			break;
-	
+
 	/* set host command */
 	outb(bIndex, SMBUS_IO_BASE+3);
-	
+
 	/* set slave address */
 	outb(devAdr | 0x01, SMBUS_IO_BASE+4);
-	
+
 	/* start */
 	outb(0x48, SMBUS_IO_BASE+2);
-	
+
 	/* SMBUS Wait Ready */
 	for ( i = 0; i < 0xFFFF; i++ )
 		if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 )
 			break;
-	
+
 	if ((sts & ~3) != 0) {
 		smbus_print_error(sts);
 		return 0;
 	}
 	bData=inb(SMBUS_IO_BASE+5);
-	
+
 	return bData;
-	
+
 }
 
-/* for reference, here is the fancier version which we will use at some 
+/* for reference, here is the fancier version which we will use at some
  * point
  */
 # if 0
@@ -203,11 +203,11 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
 {
 	unsigned char host_status_register;
 	unsigned char byte;
-	
+
 	reset();
-	
+
 	smbus_wait_until_ready();
-	
+
 	/* setup transaction */
 	/* disable interrupts */
 	outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
@@ -218,29 +218,29 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
 	/* set up for a byte data read */
 	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
 		SMBUS_IO_BASE + SMBHSTCTL);
-	
+
 	/* clear any lingering errors, so the transaction will run */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	
+
 	/* clear the data byte...*/
 	outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
-	
+
 	/* start the command */
 	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
 		SMBUS_IO_BASE + SMBHSTCTL);
-	
+
 	/* poll for transaction completion */
 	smbus_wait_until_done();
-	
+
 	host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-	
+
 	/* Ignore the In Use Status... */
 	host_status_register &= ~(1 << 6);
-	
+
 	/* read results of transaction */
 	byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
 	smbus_print_error(byte);
-	
+
 	*result = byte;
 	return host_status_register != 0x02;
 }
diff --git a/src/southbridge/via/vt8235/vt8235_ide.c b/src/southbridge/via/vt8235/vt8235_ide.c
index ec22f9053b..961f860fed 100644
--- a/src/southbridge/via/vt8235/vt8235_ide.c
+++ b/src/southbridge/via/vt8235/vt8235_ide.c
@@ -28,69 +28,69 @@ static void ide_init(struct device *dev)
 		printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n",
 				enables);
 	/* } */
-	
+
 	enables = pci_read_config8(dev, 0x40);
 	printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
 	enables |= 3;
 	pci_write_config8(dev, 0x40, enables);
 	enables = pci_read_config8(dev, 0x40);
 	printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
-	
+
 	// Enable prefetch buffers
 	enables = pci_read_config8(dev, 0x41);
 	enables |= 0xf0;
 	pci_write_config8(dev, 0x41, enables);
-	
+
 	// Lower thresholds (cause award does it)
 	enables = pci_read_config8(dev, 0x43);
 	enables &= ~0x0f;
 	enables |=  0x05;
 	pci_write_config8(dev, 0x43, enables);
-	
+
 	// PIO read prefetch counter (cause award does it)
 	pci_write_config8(dev, 0x44, 0x18);
-	
+
 	// Use memory read multiple
 	pci_write_config8(dev, 0x45, 0x1c);
-	
-	// address decoding. 
+
+	// address decoding.
 	// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
-	// kevinh@ispiri.com - the standard linux drivers seem ass slow when 
+	// kevinh@ispiri.com - the standard linux drivers seem ass slow when
 	// used in native mode - I've changed back to classic
 	enables = pci_read_config8(dev, 0x9);
 	printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
-	// by the book, set the low-order nibble to 0xa. 
+	// by the book, set the low-order nibble to 0xa.
 	if (conf->enable_native_ide) {
 		enables &= ~0xf;
-		// cf/cg silicon needs an 'f' here. 
+		// cf/cg silicon needs an 'f' here.
 		enables |= 0xf;
 	} else {
 		enables &= ~0x5;
 	}
-	
+
 	pci_write_config8(dev, 0x9, enables);
 	enables = pci_read_config8(dev, 0x9);
 	printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
-	
-	// standard bios sets master bit. 
+
+	// standard bios sets master bit.
 	enables = pci_read_config8(dev, 0x4);
 	printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
 	enables |= 7;
-	
+
 	// No need for stepping - kevinh@ispiri.com
 	enables &= ~0x80;
-	
+
 	pci_write_config8(dev, 0x4, enables);
 	enables = pci_read_config8(dev, 0x4);
 	printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
-	
+
 	if (!conf->enable_native_ide) {
 		// Use compatability mode - per award bios
 		pci_write_config32(dev, 0x10, 0x0);
 		pci_write_config32(dev, 0x14, 0x0);
 		pci_write_config32(dev, 0x18, 0x0);
 		pci_write_config32(dev, 0x1c, 0x0);
-		
+
 		// Force interrupts to use compat mode - just like Award bios
 		pci_write_config8(dev, 0x3d, 0x0);
 		pci_write_config8(dev, 0x3c, 0xff);
@@ -103,10 +103,10 @@ static struct device_operations ide_ops = {
 	.enable_resources = pci_dev_enable_resources,
 	.init             = ide_init,
 	.enable           = 0,
-	.ops_pci          = 0, 
+	.ops_pci          = 0,
 };
 
-static const struct pci_driver northbridge_driver __pci_driver = { 
+static const struct pci_driver northbridge_driver __pci_driver = {
 	.ops    = &ide_ops,
 	.vendor = PCI_VENDOR_ID_VIA,
 	.device = PCI_DEVICE_ID_VIA_82C586_1,
diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c
index 0746bc9a13..e2bfc3681e 100644
--- a/src/southbridge/via/vt8235/vt8235_lpc.c
+++ b/src/southbridge/via/vt8235/vt8235_lpc.c
@@ -88,7 +88,7 @@ static void pci_routing_fixup(struct device *dev)
 	printk(BIOS_INFO, "setting pci slot\n");
 	pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
 
-	// Cardbus slot 
+	// Cardbus slot
 	printk(BIOS_INFO, "setting cardbus slot\n");
 	pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins));
 
@@ -99,11 +99,11 @@ static void pci_routing_fixup(struct device *dev)
 	printk(BIOS_SPEW, "%s: DONE\n", __func__);
 }
 
-/* 
+/*
  * Set up the power management capabilities directly into ACPI mode.  This
  * avoids having to handle any System Management Interrupts (SMI's) which I
  * can't figure out how to do !!!!
- */ 
+ */
 
 static void setup_pm(device_t dev)
 {
@@ -112,7 +112,7 @@ static void setup_pm(device_t dev)
 
 	// Set ACPI base address to IO 0x4000
 	pci_write_config16(dev, 0x88, 0x0401);
-	
+
 	// set ACPI irq to 5
 	pci_write_config8(dev, 0x82, 0x45);
 
@@ -138,7 +138,7 @@ static void setup_pm(device_t dev)
 	outw(0xffff, 0x420);
 	outw(0xffff, 0x428);
 	outl(0xffffffff, 0x430);
-	
+
 	outw(0x0, 0x424);
 	outw(0x0, 0x42a);
 	outw(0x1, 0x42c);
@@ -152,29 +152,29 @@ static void setup_pm(device_t dev)
 static void vt8235_init(struct device *dev)
 {
 	unsigned char enables;
-	
+
 	printk(BIOS_DEBUG, "vt8235 init\n");
 
 	// enable the internal I/O decode
 	enables = pci_read_config8(dev, 0x6C);
 	enables |= 0x80;
 	pci_write_config8(dev, 0x6C, enables);
-	
+
 	// Map 4MB of FLASH into the address space
 	pci_write_config8(dev, 0x41, 0x7f);
-	
+
 	// Set bit 6 of 0x40, because Award does it (IO recovery time)
-	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI 
+	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
 	// interrupts can be properly marked as level triggered.
 	enables = pci_read_config8(dev, 0x40);
 	enables |= 0x45;
 	pci_write_config8(dev, 0x40, enables);
-	
+
 	// Set 0x42 to 0xf0 to match Award bios
 	enables = pci_read_config8(dev, 0x42);
 	enables |= 0xf0;
 	pci_write_config8(dev, 0x42, enables);
-	
+
 	/* Set 0x58 to 0x03 to match Award */
 	pci_write_config8(dev, 0x58, 0x03);
 
@@ -187,16 +187,16 @@ static void vt8235_init(struct device *dev)
 	enables = pci_read_config8(dev, 0x4a);
 	enables |= 0x08;
 	pci_write_config8(dev, 0x4a, enables);
-	
+
 	// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
 	enables = pci_read_config8(dev, 0x4f);
 	enables |= 0x08;
 	pci_write_config8(dev, 0x4f, enables);
-	
+
 	// Set 0x58 to 0x03 to match Award
 	pci_write_config8(dev, 0x58, 0x03);
-	
-	
+
+
 	/* enable serial irq */
 	pci_write_config8(dev, 0x52, 0x9);
 
@@ -205,10 +205,10 @@ static void vt8235_init(struct device *dev)
 
 	// Power management setup
 	setup_pm(dev);
-	
+
 	/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
 	pci_write_config8(dev, 0x40, 0x54);
-	
+
 	// Start the rtc
 	rtc_init(0);
 }
@@ -248,7 +248,7 @@ static void vt8235_enable_resources(device_t dev)
 	pci_dev_enable_resources(dev);
 	enable_childrens_resources(dev);
 }
-	
+
 static void southbridge_init(struct device *dev)
 {
 	vt8235_init(dev);
diff --git a/src/southbridge/via/vt8235/vt8235_nic.c b/src/southbridge/via/vt8235/vt8235_nic.c
index 86fef895de..71f169c055 100644
--- a/src/southbridge/via/vt8235/vt8235_nic.c
+++ b/src/southbridge/via/vt8235/vt8235_nic.c
@@ -5,7 +5,7 @@
 #include <device/pci_ids.h>
 
 /*
- * Enable the ethernet device and turn off stepping (because it is integrated 
+ * Enable the ethernet device and turn off stepping (because it is integrated
  * inside the southbridge)
  */
 static void nic_init(struct device *dev)
diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
index aa75f50651..9f824437bf 100644
--- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
+++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
@@ -171,10 +171,10 @@ void enable_smbus(void)
 }
 
 /**
- * A fixup for some systems that need time for the SMBus to "warm up". This is 
- * needed on some VT823x based systems, where the SMBus spurts out bad data for 
- * a short time after power on. This has been seen on the VIA Epia series and 
- * Jetway J7F2-series. It reads the ID byte from SMBus, looking for 
+ * A fixup for some systems that need time for the SMBus to "warm up". This is
+ * needed on some VT823x based systems, where the SMBus spurts out bad data for
+ * a short time after power on. This has been seen on the VIA Epia series and
+ * Jetway J7F2-series. It reads the ID byte from SMBus, looking for
  * known-good data from a slot/address. Exits on either good data or a timeout.
  *
  * TODO: This should probably go into some global file, but one would need to
diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c
index f7acb75766..5a08e3b16f 100644
--- a/src/southbridge/via/vt8237r/vt8237r_lpc.c
+++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c
@@ -187,7 +187,7 @@ static void setup_pm(device_t dev)
 	 * 6 = SUSST# Deasserted Before PWRGD for STD
 	 * 5 = Keyboard/Mouse Swap
 	 * 4 = PWRGOOD reset on VT8237A/S
-	 * 3 = GPO26/GPO27 is GPO 
+	 * 3 = GPO26/GPO27 is GPO
 	 * 2 = Disable Alert on Lan
 	 * 1 = SUSCLK/GPO4
 	 * 0 = USB Wakeup
@@ -247,7 +247,7 @@ static void setup_pm(device_t dev)
 static void vt8237r_init(struct device *dev)
 {
 	u8 enables;
-	
+
 #if CONFIG_EPIA_VT8237R_INIT
 	printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");
 	/*
@@ -260,9 +260,9 @@ static void vt8237r_init(struct device *dev)
 	enables = pci_read_config8(dev, 0xe5);
 	enables |= 0x23;
 	pci_write_config8(dev, 0xe5, enables);
-	
-	/* 
-	 * Enable Flash Write Access. 
+
+	/*
+	 * Enable Flash Write Access.
 	 * Note EPIA-N Does not use REQ5 or PCISTP#(Hang)
 	 */
 	enables = pci_read_config8(dev, 0xe4);
@@ -274,14 +274,14 @@ static void vt8237r_init(struct device *dev)
 	enables |= 0x80;
 	pci_write_config8(dev, 0x4E, enables);
 
-#else 
+#else
 	printk(BIOS_SPEW, "Entering vt8237r_init.\n");
 	/*
 	 * Enable SATA LED, disable special CPU Frequency Change -
 	 * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs.
 	 */
 	pci_write_config8(dev, 0xe5, 0x09);
-	
+
 	/* REQ5 as PCI request input - should be together with INTE-INTH. */
 	pci_write_config8(dev, 0xe4, 0x4);
 #endif
@@ -329,7 +329,7 @@ static void vt8237s_init(struct device *dev)
 			   (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
 
 	/*
-	 * REQ5 as PCI request input - should be together with INTE-INTH. 
+	 * REQ5 as PCI request input - should be together with INTE-INTH.
 	 */
 	pci_write_config8(dev, 0xe4, 0x04);