Extended K8T890 driver to include the K8T800 and K8M800 northbridges

The K8T800 is almost identical to the K8T800Pro, also added to this patch.
The K8T800_OLD is also defined, which is an older version of the K8T800,
but which has no driver and early HT code yet. Also extended the K8M890 VGA
driver to work for the K8M800 (not tested). According to the datasheet, the
K8T890 and K8T800 are similar enough to be able to use the same
initialization code. At least for the K8T800, this is sufficient to have
a working HT link with the CPU, and to initialise the V-Link to the
southbridge.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 44 insertions, 6 deletions

diff --git a/src/southbridge/via/vt8237r/ctrl.c b/src/southbridge/via/vt8237r/ctrl.c
index f3cc30ed88..b268ad54e9 100644
--- a/src/southbridge/via/vt8237r/ctrl.c
+++ b/src/southbridge/via/vt8237r/ctrl.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -32,7 +33,13 @@ static void vt8237_cfg(struct device *dev)
 	device_t devfun3;
 
 	devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
-				  PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
+				  PCI_DEVICE_ID_VIA_K8T800_DRAM, 0);
+	if (!devfun3)
+		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8M800_DRAM, 0);
+	if (!devfun3)
+	  devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
+				    PCI_DEVICE_ID_VIA_K8T890CE_3, 0);
 	if (!devfun3)
 		devfun3 = dev_find_device(PCI_VENDOR_ID_VIA,
 					  PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
@@ -108,7 +115,13 @@ static void vt8237s_vlink_init(struct device *dev)
 	device_t devfun7;
 
 	devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
-				  PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+				  PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
 	if (!devfun7)
 		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
 					  PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
@@ -117,7 +130,10 @@ static void vt8237s_vlink_init(struct device *dev)
 					  PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
 	/* No pairing NB was found. */
 	if (!devfun7)
+	{
+		print_debug("vt8237s_vlink_init: No pairing NB was found.\n");
 		return;
+	}
 
 	/*
 	 * This init code is valid only for the VT8237S! For different
@@ -174,7 +190,13 @@ static void vt8237a_vlink_init(struct device *dev)
 	device_t devfun7;
 
 	devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
-				  PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
+				  PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, 0);
+	if (!devfun7)
+		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
+					  PCI_DEVICE_ID_VIA_K8T890CE_7, 0);
 	if (!devfun7)
 		devfun7 = dev_find_device(PCI_VENDOR_ID_VIA,
 					  PCI_DEVICE_ID_VIA_K8M890CE_7, 0);
@@ -183,7 +205,10 @@ static void vt8237a_vlink_init(struct device *dev)
 					  PCI_DEVICE_ID_VIA_K8T890CF_7, 0);
 	/* No pairing NB was found. */
 	if (!devfun7)
+	{
+		print_debug("vt8237a_vlink_init: No pairing NB was found.\n");
 		return;
+	}
 
 	/*
 	 * This init code is valid only for the VT8237A! For different
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 3ffc377572..61f4989f54 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -299,11 +299,20 @@ static void vt8237r_init(struct device *dev)
 	 */
 	pci_write_config8(dev, 0x48, 0x0c);
 #else
+	
+  #if CONFIG_SOUTHBRIDGE_VIA_K8T800
+	/* It seems that when we pair with the K8T800, we need to disable
+	 * the A2 mask
+	 */
+	pci_write_config8(dev, 0x48, 0x0c);
+  #else
 	/*
 	 * Set Read Pass Write Control Enable
 	 * (force A2 from APIC FSB to low).
 	 */
 	pci_write_config8(dev, 0x48, 0x8c);
+  #endif
+	
 #endif
 
 	southbridge_init_common(dev);
@@ -319,6 +328,8 @@ static void vt8237r_init(struct device *dev)
 #endif
 
 	printk(BIOS_SPEW, "Leaving %s.\n", __func__);
+	printk(BIOS_SPEW, "And taking a dump:\n");
+	dump_south(dev);	
 }
 
 static void vt8237a_init(struct device *dev)
@@ -469,6 +480,7 @@ static void vt8237_common_init(struct device *dev)
 	 * Bit | Meaning
 	 * -------------
 	 *   3 | Bypass APIC De-Assert Message (1=Enable)
+	 *   2 | APIC HyperTransport Mode (1=Enable)
 	 *   1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
 	 *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
 	 *   0 | Dynamic Clock Gating Main Switch (1=Enable)
@@ -485,12 +497,13 @@ static void vt8237_common_init(struct device *dev)
 	pci_write_config8(dev, 0x4c, 0x44);
 
 	/* ROM memory cycles go to LPC. */
-	pci_write_config8(dev, 0x59, 0x80);
+ 	pci_write_config8(dev, 0x59, 0x80);
 
 	/*
 	 * Bit | Meaning
 	 * -------------
 	 *   3 | Bypass APIC De-Assert Message (1=Enable)
+	 *   2 | APIC HyperTransport Mode (1=Enable)
 	 *   1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI"
 	 *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
 	 *   0 | Dynamic Clock Gating Main Switch (1=Enable)
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index be24bb5dc2..5ba3815145 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -40,9 +40,9 @@ void writeback(struct device *dev, u16 where, u8 what)
 	if (regval != what) {
 		print_debug("Writeback to ");
 		print_debug_hex8(where);
-		print_debug("failed ");
+		print_debug(" failed ");
 		print_debug_hex8(regval);
-		print_debug("\n ");	/* TODO: Drop the space? */
+		print_debug("\n");
 	}
 }
 #else