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authorBari Ari <bari@onelabs.com>2008-09-01 01:48:07 +0000
committerPeter Stuge <peter@stuge.se>2008-09-01 01:48:07 +0000
commitd4759d0f22892cc740d5aae559eaf5b9b5ab735a (patch)
treeadbd541327d47654590814029eb3493d2e5deef3 /src/southbridge/via/vt8237r/vt8237r.c
parent3153863567f51c9173227b9cb4375d53e6f3e6ed (diff)
This patch gets the Epia-CN working without ACPI or APIC.
All devices work, no irq storms. Enjoy. Signed-off-by: Bari Ari <bari@onelabs.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via/vt8237r/vt8237r.c')
-rw-r--r--src/southbridge/via/vt8237r/vt8237r.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index 9b85f2fc32..a72b9a1c06 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -79,8 +79,6 @@ static void vt8237r_enable(struct device *dev)
pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);
/* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */
- /* Extend ROM decode to 1MB FFC00000 - FFFFFFFF */
- pci_write_config8(dev, 0x41, 0x7f);
}
struct chip_operations southbridge_via_vt8237r_ops = {