diff options
| author | Florian Zumbiehl <florz@florz.de> | 2011-11-01 20:16:16 +0100 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-11-07 13:04:36 +0100 |
| commit | 86bb0072b6201875190c5ec78f5415cd51a9e115 (patch) | |
| tree | e9783eb7617882c57d49ea36e477fe92572b612b /src/southbridge/via/vt8237r/vt8237r.c | |
| parent | 7e9de01c4758cc1e8adb05d0c443701495e98fe0 (diff) | |
in vt8237r_enable(), write function enables only to ISA bridge config space
vt8237r_enable() so far wrote the function enable values to the same
offset in the config space of every one of the vt8237's functions,
even though the register is located in the ISA bridge only.
Change-Id: I639586dc238132f5b8d2f320b794948718281b9c
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/368
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/via/vt8237r/vt8237r.c')
| -rw-r--r-- | src/southbridge/via/vt8237r/vt8237r.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index 5ba3815145..586df66b8e 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -66,11 +66,21 @@ void dump_south(device_t dev) static void vt8237r_enable(struct device *dev) { + u16 vid, did; struct southbridge_via_vt8237r_config *sb = (struct southbridge_via_vt8237r_config *)dev->chip_info; - pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); - pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + if (dev->path.type == DEVICE_PATH_PCI) { + vid = pci_read_config16(dev, PCI_VENDOR_ID); + did = pci_read_config16(dev, PCI_DEVICE_ID); + if (vid == PCI_VENDOR_ID_VIA && + (did == PCI_DEVICE_ID_VIA_VT8237R_LPC || + did == PCI_DEVICE_ID_VIA_VT8237A_LPC || + did == PCI_DEVICE_ID_VIA_VT8237S_LPC)) { + pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); + pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + } + } /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ } |