Following patch adds K8M890 support. It initializes the AGP and graphics UMA.

The V-link setup and HT bridge is redone, because VT8237A has it in another
device. So far following combination of chipsets should now work:

K8T890CE + VT8237R
K8M890(CE) + VT8237R

VIA PC1 brige moved to NB code (vt8237r_bridge.c -> k8t890_bridge.c) and
notes about K8M890 support were added.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 41 insertions, 3 deletions

diff --git a/src/southbridge/via/k8t890/k8t890_host.c b/src/southbridge/via/k8t890/k8t890_host.c
index 2ab16f58a2..d91b8f3b95 100644
--- a/src/southbridge/via/k8t890/k8t890_host.c
+++ b/src/southbridge/via/k8t890/k8t890_host.c
@@ -28,9 +28,32 @@ static void host_enable(struct device *dev)
 {
 	/* Multiple function control */
 	pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
+
+}
+
+
+static void host_init(struct device *dev)
+{
+	u8 reg;
+
+	/* AGP Capability Header Control */
+	reg = pci_read_config8(dev, 0x4d);
+	reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */
+	pci_write_config8(dev, 0x4d, reg);
+
+	/* GD Output Stagger Delay */
+	reg = pci_read_config8(dev, 0x42);
+	reg |= 0x10; /* AD[31:16] with 1ns */
+	pci_write_config8(dev, 0x42, reg);
+
+	/* AGP Control */
+	reg = pci_read_config8(dev, 0xbc);
+	reg |= 0x20; /* AGP Read Snoop DRAM Post-Write Buffer */
+	pci_write_config8(dev, 0xbc, reg);
+
 }
 
-static const struct device_operations host_ops = {
+static const struct device_operations host_ops_t = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
@@ -38,8 +61,23 @@ static const struct device_operations host_ops = {
 	.ops_pci		= 0,
 };
 
-static const struct pci_driver northbridge_driver __pci_driver = {
-	.ops	= &host_ops,
+static const struct device_operations host_ops_m = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.enable			= host_enable,
+	.init			= host_init,
+	.ops_pci		= 0,
+};
+
+static const struct pci_driver northbridge_driver_t __pci_driver = {
+	.ops	= &host_ops_t,
 	.vendor	= PCI_VENDOR_ID_VIA,
 	.device	= PCI_DEVICE_ID_VIA_K8T890CE_0,
 };
+
+static const struct pci_driver northbridge_driver_m __pci_driver = {
+	.ops	= &host_ops_m,
+	.vendor	= PCI_VENDOR_ID_VIA,
+	.device	= PCI_DEVICE_ID_VIA_K8M890CE_0,
+};