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| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2017-09-07 12:15:45 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-11 21:26:27 +0000 |
| commit | b051a9f5348abab842748577eaf4f06418df0ba3 (patch) | |
| tree | 139e0c4938baa9b998c107642a45e78c613442b1 /src/southbridge/ti | |
| parent | bfabe62a6e5cdd9e29394b12737c5ed9bd080036 (diff) | |
soc/intel/skylake: Fix SPI WP disable status check
Use SPI write protect disable bit from BIOS_CONTROL register
to check write protect status.
Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/21449
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/ti')
0 files changed, 0 insertions, 0 deletions