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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-17 16:32:24 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-18 14:55:35 +0000 |
| commit | 569887a64084f18da1daf55ff0f10a855bb537c8 (patch) | |
| tree | ca09e087af5ee5da84491f3baa08813cf5e61654 /src/southbridge/ti | |
| parent | fb57d7c54931376a2ec751df521954b900e7730c (diff) | |
soc/intel/common: lpc/espi: fix wrong lock bit
This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance
with doc#332691-003EN and doc#334819-001.
Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/ti')
0 files changed, 0 insertions, 0 deletions