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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-06-04 13:43:32 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 08:40:16 +0000 |
| commit | aa5e8e099e83647cd6347bcbc82e2c11a6cac1d7 (patch) | |
| tree | 31fa45febdf749472325be5f00c57520bba40229 /src/southbridge/ti/pci7420 | |
| parent | 37fedc0414af6e5e2daccef5caa4b37632699f15 (diff) | |
siemens/mc_apl5: Change PTN interface settings
Switch the default clock output for single LVDS mode to odd bus only.
Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/southbridge/ti/pci7420')
0 files changed, 0 insertions, 0 deletions