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author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2018-03-16 14:32:06 -0700 |
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committer | Martin Roth <martinroth@google.com> | 2018-03-21 18:24:26 +0000 |
commit | 445d553af805c5ce50527513ae6889a3f9b4a22a (patch) | |
tree | 1b018f6cafdba8ab88da6d280e29270aaa4bd12b /src/southbridge/ti/pci1x2x | |
parent | 4a664fa61ba91117921e4b70f9e14917b0ca7ce9 (diff) |
mb/google/octopus: Re-size flash WP_RO segment
Update the size in WP_RO segment of the flash to accommodate builds using
debug FSP.
Change-Id: I0a0d1d0121b503ff390adf3ce25973d72e59fdeb
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/25253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/ti/pci1x2x')
0 files changed, 0 insertions, 0 deletions