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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2017-10-30 17:20:18 +0100
committerMartin Roth <martinroth@google.com>2017-11-04 00:33:26 +0000
commit0781cbe1d33e62a26a234962bc271209cc22c931 (patch)
tree99aca77e0aab82cd3c869f333a6ff33fd63f391d /src/southbridge/ti/pci1x2x
parent7bd4715a7016b3228df877d625cf26a3694cfebe (diff)
sb and soc: Enforce correct offset of member "chromeos" in global_nvs_t
The padding has recently been broken in commit 90ebf96df5 ("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset for chromeos"). Avoid this bug in the future. Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/ti/pci1x2x')
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