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author | Felix Held <felix-coreboot@felixheld.de> | 2015-11-06 18:32:43 +0100 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-19 02:43:23 +0100 |
commit | df95b51ab636f78f66c27d7a7b0aebf245f288c1 (patch) | |
tree | 970d2e6ac1b46684cb0e142d6b81676a6c5ff995 /src/southbridge/sis | |
parent | b06015b92ec0a44646d18ec32f2cb333e965e616 (diff) |
pcengines/apu1: enable use of clkreq pins
only enable pcie gpp clocks when the corresponding clkreq pin is asserted
Change-Id: I7822d011bb94867d470c0194e6b652833c395cb2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12353
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/sis')
0 files changed, 0 insertions, 0 deletions