src/southbridge: Code formating

Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

10 files changed, 402 insertions, 426 deletions

diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c
index dfd146d6ff..9c05cb13b1 100644
--- a/src/southbridge/sis/sis966/aza.c
+++ b/src/southbridge/sis/sis966/aza.c
@@ -56,7 +56,7 @@ static int set_bits(void *port, u32 mask, u32 val)
 		udelay(100);
 	} while ((dword != val) && --count);
 
-	if(!count) return -1;
+	if (!count) return -1;
 
 	udelay(500);
 	return 0;
@@ -98,9 +98,9 @@ static int codec_detect(u8 *base)
 
 	set_bits(base + 0x08, 1, 1);
 
-      do{
+      do {
 	  	dword = read32(base + 0x08)&0x1;
-		if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;}
+		if (idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;}
 	   } while (dword !=1);
 
        dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId
@@ -184,7 +184,7 @@ static u32 verb_data[] = {
 
 static unsigned find_verb(u32 viddid, u32 **verb)
 {
-        if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
+	if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
 	*verb =  (u32 *)verb_data;
 	return sizeof(verb_data)/sizeof(u32);
 }
@@ -215,14 +215,14 @@ static void codec_init(u8 *base, int addr)
 	printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
 	verb_size = find_verb(dword, &verb);
 
-	if(!verb_size) {
+	if (!verb_size) {
 		printk(BIOS_DEBUG, "No verb!\n");
 		return;
 	}
 
 	printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
 	/* 3 */
-	for(i=0; i<verb_size; i++) {
+	for (i=0; i<verb_size; i++) {
 		send_verb(base,verb[i]);
 	}
 	printk(BIOS_DEBUG, "verb loaded!\n");
@@ -236,50 +236,50 @@ static void codecs_init(u8 *base, u32 codec_mask)
 
 static void aza_init(struct device *dev)
 {
-        u8 *base;
-        struct resource *res;
-        u32 codec_mask;
+	u8 *base;
+	struct resource *res;
+	u32 codec_mask;
 
-        printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n");
+	printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n");
 
 //-------------- enable AZA (SiS7502) -------------------------
 {
-        u8  temp8;
-        int i=0;
-        while(SiS_SiS7502_init[i][0] != 0)
-        {
-                temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
-                temp8 &= SiS_SiS7502_init[i][1];
-                temp8 |= SiS_SiS7502_init[i][2];
-                pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
-                i++;
-        };
+	u8  temp8;
+	int i=0;
+	while (SiS_SiS7502_init[i][0] != 0)
+	{
+		temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
+		temp8 &= SiS_SiS7502_init[i][1];
+		temp8 |= SiS_SiS7502_init[i][2];
+		pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
+		i++;
+	};
 }
 //-----------------------------------------------------------
 
 
-        // put audio to D0 state
-        pci_write_config8(dev, 0x54,0x00);
+	// put audio to D0 state
+	pci_write_config8(dev, 0x54,0x00);
 
 #if DEBUG_AZA
 {
-        int i;
-
-        printk(BIOS_DEBUG, "****** Azalia PCI config ******");
-        printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
-
-        for (i=0;i<0xff;i+=4){
-                if ((i%16)==0){
-                        printk(BIOS_DEBUG, "\n%02x: ", i);
-                }
-                printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
-        }
-        printk(BIOS_DEBUG, "\n");
+	int i;
+
+	printk(BIOS_DEBUG, "****** Azalia PCI config ******");
+	printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+	for (i=0;i<0xff;i+=4){
+		if ((i%16)==0){
+			printk(BIOS_DEBUG, "\n%02x: ", i);
+		}
+		printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
+	}
+	printk(BIOS_DEBUG, "\n");
 }
 #endif
 
 	res = find_resource(dev, 0x10);
-	if(!res)
+	if (!res)
 		return;
 
 	base = res2mmio(res, 0, 0);
@@ -287,12 +287,12 @@ static void aza_init(struct device *dev)
 
 	codec_mask = codec_detect(base);
 
-	if(codec_mask) {
+	if (codec_mask) {
 		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
 		codecs_init(base, codec_mask);
 	}
 
-        printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n");
+	printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n");
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/sis/sis966/early_setup_car.c b/src/southbridge/sis/sis966/early_setup_car.c
index b9ee592ed1..ba6d8a3124 100644
--- a/src/southbridge/sis/sis966/early_setup_car.c
+++ b/src/southbridge/sis/sis966/early_setup_car.c
@@ -29,7 +29,7 @@ void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io
 	dword |= 0x3f0; // disable it at first
 	pci_write_config32(dev, 0xe4, dword);
 
-	for(i=0; i<3; i++) {
+	for (i=0; i<3; i++) {
 		tgio_ctrl = inl(anactrl_io_base + 0xcc);
 		tgio_ctrl &= ~(3<<9);
 		tgio_ctrl |= (i<<9);
diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c
index 15d4f4ceef..4a2b867855 100644
--- a/src/southbridge/sis/sis966/early_smbus.c
+++ b/src/southbridge/sis/sis966/early_smbus.c
@@ -37,7 +37,7 @@ int smbus_wait_until_ready(unsigned smbus_io_base)
 			return 0;
 		}
 		outb(val,smbus_io_base + SMBHSTSTAT);
-	} while(--loops);
+	} while (--loops);
 	return -2;
 }
 
@@ -53,7 +53,7 @@ int smbus_wait_until_done(unsigned smbus_io_base)
 		if ( (val & 0xff) != 0x02) {
 			return 0;
 		}
-	} while(--loops);
+	} while (--loops);
 	return -3;
 }
 
@@ -135,11 +135,10 @@ static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, un
 	smbus_delay();
 
 	int i, j;
-	for(i = 0;i < 0x1000; i++)
-	{
-		if (inb(smbus_io_base + 0x00) != 0x08)
-		{	smbus_delay();
-			for(j=0;j<0xFFFF;j++);
+	for (i = 0;i < 0x1000; i++) {
+		if (inb(smbus_io_base + 0x00) != 0x08) {
+			smbus_delay();
+			for (j=0;j<0xFFFF;j++);
 		}
 	}
 
@@ -502,12 +501,13 @@ static const uint8_t	SiS_SiS1183_init[44][3]={
 };
 
 /*       In => Share Memory size
-                            => 00h :    0MBytes
-                            => 02h :   32MBytes
-                            => 03h :   64MBytes
-                            => 04h :  128MBytes
-                            => Others:  Reserved
-*/
+ *                           => 00h :    0MBytes
+ *                           => 02h :   32MBytes
+ *                           => 03h :   64MBytes
+ *                           => 03h :   64MBytes
+ *                           => 04h :  128MBytes
+ *                           => Others:  Reserved
+ */
 static void Init_Share_Memory(uint8_t ShareSize)
 {
     device_t dev;
@@ -517,62 +517,62 @@ static void Init_Share_Memory(uint8_t ShareSize)
 }
 
 /* In:     => Aperture size
-               => 00h :   32MBytes
-               => 01h :   64MBytes
-               => 02h :  128MBytes
-               => 03h :  256MBytes
-               => 04h :  512MBytes
-               => Others:  Reserved
-*/
+ *              => 00h :   32MBytes
+ *              => 01h :   64MBytes
+ *              => 02h :  128MBytes
+ *              => 03h :  256MBytes
+ *              => 04h :  512MBytes
+ *              => Others:  Reserved
+ */
 static void Init_Aper_Size(uint8_t AperSize)
 {
-        device_t dev;
-        uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
+	device_t dev;
+	uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
 
-        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
-        pci_write_config8(dev, 0x90, AperSize << 1);
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
+	pci_write_config8(dev, 0x90, AperSize << 1);
 
-        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
-        pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
+	pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
 }
 
 static void sis_init_stage1(void)
 {
-        device_t dev;
-        uint8_t temp8;
-        int	i;
-        uint8_t	GUI_En;
+	device_t dev;
+	uint8_t temp8;
+	int	i;
+	uint8_t	GUI_En;
 
 // SiS_Chipset_Initialization
 // ========================== NB =============================
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
 	i=0;
-	while(SiS_NB_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_NB_init[i][0]);
-					temp8 &= SiS_NB_init[i][1];
-					temp8 |= SiS_NB_init[i][2];
-					pci_write_config8(dev, SiS_NB_init[i][0], temp8);
-					i++;
+	while (SiS_NB_init[i][0] != 0) {
+		temp8 = pci_read_config8(dev, SiS_NB_init[i][0]);
+		temp8 &= SiS_NB_init[i][1];
+		temp8 |= SiS_NB_init[i][2];
+		pci_write_config8(dev, SiS_NB_init[i][0], temp8);
+		i++;
 	};
 
 // ========================== LPC =============================
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 	i=0;
-	while(SiS_LPC_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]);
-					temp8 &= SiS_LPC_init[i][1];
-					temp8 |= SiS_LPC_init[i][2];
-					pci_write_config8(dev, SiS_LPC_init[i][0], temp8);
-					i++;
+	while (SiS_LPC_init[i][0] != 0) {
+		temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]);
+		temp8 &= SiS_LPC_init[i][1];
+		temp8 |= SiS_LPC_init[i][2];
+		pci_write_config8(dev, SiS_LPC_init[i][0], temp8);
+		i++;
 	};
 // ========================== ACPI =============================
 	i=0;
-	while(SiS_ACPI_init[i][0] != 0)
-	{				temp8 = inb(0x800 + SiS_ACPI_init[i][0]);
-					temp8 &= SiS_ACPI_init[i][1];
-					temp8 |= SiS_ACPI_init[i][2];
-					outb(temp8, 0x800 + SiS_ACPI_init[i][0]);
-					i++;
+	while (SiS_ACPI_init[i][0] != 0) {
+		temp8 = inb(0x800 + SiS_ACPI_init[i][0]);
+		temp8 &= SiS_ACPI_init[i][1];
+		temp8 |= SiS_ACPI_init[i][2];
+		outb(temp8, 0x800 + SiS_ACPI_init[i][0]);
+		i++;
 	};
 // ========================== NBPCIE =============================
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);	//Disable Internal GUI enable bit
@@ -582,12 +582,12 @@ static void sis_init_stage1(void)
 
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761_PCIE), 0);
 	i=0;
-	while(SiS_NBPCIE_init[i][0] != 0)
-	{				temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]);
-					temp8 &= SiS_NBPCIE_init[i][1];
-					temp8 |= SiS_NBPCIE_init[i][2];
-					pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8);
-					i++;
+	while (SiS_NBPCIE_init[i][0] != 0) {
+		temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]);
+		temp8 &= SiS_NBPCIE_init[i][1];
+		temp8 |= SiS_NBPCIE_init[i][2];
+		pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8);
+		i++;
 	};
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);	//Restore Internal GUI enable bit
 	temp8 = pci_read_config8(dev, 0x4C);
@@ -608,20 +608,19 @@ static void sis_init_stage2(void)
 
 
 // ========================== NB_AGP =============================
-        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);   //Enable Internal GUI enable bit
-        pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);   //Enable Internal GUI enable bit
+	pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
 
-        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
-        i=0;
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
+	i=0;
 
-        while(SiS_NBAGP_init[i][0] != 0)
-        {
-                temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
-                temp8 &= SiS_NBAGP_init[i][1];
-                temp8 |= SiS_NBAGP_init[i][2];
-                pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
-                i++;
-        };
+	while (SiS_NBAGP_init[i][0] != 0) {
+		temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
+		temp8 &= SiS_NBAGP_init[i][1];
+		temp8 |= SiS_NBAGP_init[i][2];
+		pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
+		i++;
+	};
 
 /**
   *   Share Memory size
@@ -640,38 +639,38 @@ static void sis_init_stage2(void)
   *             => Others:  Reserved
   */
 
-        Init_Share_Memory(0x02);  //0x02 : 32M
-        Init_Aper_Size(0x01);   //0x1 : 64M
+	Init_Share_Memory(0x02);  //0x02 : 32M
+	Init_Aper_Size(0x01);   //0x1 : 64M
 
 // ========================== NB =============================
 
-        printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n");
-        dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
-        msr = rdmsr(0xC001001A);
+	printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n");
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
+	msr = rdmsr(0xC001001A);
 	 printk(BIOS_DEBUG, "Memory Top Bound %x\n",msr.lo );
 
-        temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
-        temp16=0x0001<<(temp16-1);
-        temp16<<=8;
+	temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
+	temp16=0x0001<<(temp16-1);
+	temp16<<=8;
 
-        printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
-        pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
-        pci_write_config8(dev, 0x7F, 0x08);									// ACPI Base
-        outb(inb(0x856) | 0x40, 0x856);										// Auto-Reset Function
+	printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
+	pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
+	pci_write_config8(dev, 0x7F, 0x08);									// ACPI Base
+	outb(inb(0x856) | 0x40, 0x856);										// Auto-Reset Function
 
 // ========================== ACPI =============================
 	i=0;
 	printk(BIOS_DEBUG, "Init ACPI -------->\n");
-	do
-	{				temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
-					temp8 &= SiS_ACPI_2_init[i][1];
-					temp8 |= SiS_ACPI_2_init[i][2];
-					outb(temp8, 0x800 + SiS_ACPI_2_init[i][0]);
-					i++;
-	}while(SiS_ACPI_2_init[i][0] != 0);
+	do {
+		temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
+		temp8 &= SiS_ACPI_2_init[i][1];
+		temp8 |= SiS_ACPI_2_init[i][2];
+		outb(temp8, 0x800 + SiS_ACPI_2_init[i][0]);
+		i++;
+	} while (SiS_ACPI_2_init[i][0] != 0);
 
 // ========================== Misc =============================
-       printk(BIOS_DEBUG, "Init Misc -------->\n");
+	printk(BIOS_DEBUG, "Init Misc -------->\n");
 	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
 
 	/* R77h Internal PCI Device Enable 1 (Power On Value = 0h)
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c
index ebea6f3d70..56862270cc 100644
--- a/src/southbridge/sis/sis966/ide.c
+++ b/src/southbridge/sis/sis966/ide.c
@@ -101,15 +101,14 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
 
 //-------------- enable IDE (SiS5513) -------------------------
 {
-        uint8_t  temp8;
-        int i=0;
-	while(SiS_SiS5513_init[i][0] != 0)
-	{
-                temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
-                temp8 &= SiS_SiS5513_init[i][1];
-                temp8 |= SiS_SiS5513_init[i][2];
-                pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
-                i++;
+	uint8_t  temp8;
+	int i=0;
+	while (SiS_SiS5513_init[i][0] != 0) {
+		temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
+		temp8 &= SiS_SiS5513_init[i][1];
+		temp8 |= SiS_SiS5513_init[i][2];
+		pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
+		i++;
 	};
 }
 //-----------------------------------------------------------
@@ -143,17 +142,17 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
 
 #if DEBUG_IDE
 {
-        int i;
+	int i;
 
-        printk(BIOS_DEBUG, "****** IDE PCI config ******");
-        printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
+	printk(BIOS_DEBUG, "****** IDE PCI config ******");
+	printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
 
-        for (i=0;i<0xff;i+=4){
-                if ((i%16)==0)
-                        printk(BIOS_DEBUG, "\n%02x: ", i);
-                printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
-        }
-        printk(BIOS_DEBUG, "\n");
+	for (i=0;i<0xff;i+=4) {
+		if ((i%16)==0)
+			printk(BIOS_DEBUG, "\n%02x: ", i);
+		printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
+	}
+	printk(BIOS_DEBUG, "\n");
 }
 #endif
 printk(BIOS_DEBUG, "IDE_INIT:<----------\n");
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index ef26745dbc..e1a356ba5f 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -112,7 +112,7 @@ static void lpc_init(device_t dev)
 	/* Throttle the CPU speed down for testing */
 	on = SLOW_CPU_OFF;
 	get_option(&on, "slow_cpu");
-	if(on) {
+	if (on) {
 		uint16_t pm10_bar;
 		uint32_t dword;
 		pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
@@ -123,33 +123,33 @@ static void lpc_init(device_t dev)
 				(on*12)+(on>>1),(on&1)*5);
 	}
 
-        /* Enable Error reporting */
-        /* Set up sync flood detected */
-        byte = pci_read_config8(dev, 0x47);
-        byte |= (1 << 1);
-        pci_write_config8(dev, 0x47, byte);
-
-        /* Set up NMI on errors */
-        byte = inb(0x70); // RTC70
-        byte_old = byte;
-        nmi_option = NMI_OFF;
-        get_option(&nmi_option, "nmi");
-        if (nmi_option) {
-                byte &= ~(1 << 7); /* set NMI */
-        } else {
-                byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
-        }
-        if ( byte != byte_old) {
-                outb(byte, 0x70);
-        }
-
-        /* Initialize the real time clock */
-        cmos_init(0);
-
-        /* Initialize isa dma */
-        isa_dma_init();
-
-        printk(BIOS_DEBUG, "LPC_INIT <--------\n");
+	/* Enable Error reporting */
+	/* Set up sync flood detected */
+	byte = pci_read_config8(dev, 0x47);
+	byte |= (1 << 1);
+	pci_write_config8(dev, 0x47, byte);
+
+	/* Set up NMI on errors */
+	byte = inb(0x70); // RTC70
+	byte_old = byte;
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		byte &= ~(1 << 7); /* set NMI */
+	} else {
+		byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
+	}
+	if ( byte != byte_old) {
+		outb(byte, 0x70);
+	}
+
+	/* Initialize the real time clock */
+	cmos_init(0);
+
+	/* Initialize isa dma */
+	isa_dma_init();
+
+	printk(BIOS_DEBUG, "LPC_INIT <--------\n");
 }
 
 static void sis966_lpc_read_resources(device_t dev)
@@ -195,11 +195,11 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
 	for (link = dev->link_list; link; link = link->next) {
 		device_t child;
 		for (child = link->children; child; child = child->sibling) {
-			if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
+			if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 				struct resource *res;
-				for(res = child->resource_list; res; res = res->next) {
+				for (res = child->resource_list; res; res = res->next) {
 					unsigned long base, end; // don't need long long
-					if(!(res->flags & IORESOURCE_IO)) continue;
+					if (!(res->flags & IORESOURCE_IO)) continue;
 					base = res->base;
 					end = resource_end(res);
 					printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
@@ -217,8 +217,8 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
 					case 0x300:  // Midi 0
 						reg |= (1<<12);	break;
 					}
-					if( (base == 0x290) || (base >= 0x400)) {
-						if(var_num>=4) continue; // only 4 var ; compact them ?
+					if ( (base == 0x290) || (base >= 0x400)) {
+						if (var_num>=4) continue; // only 4 var ; compact them ?
 						reg |= (1<<(28+var_num));
 						reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
 					}
@@ -227,7 +227,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
 		}
 	}
 	pci_write_config32(dev, 0xa0, reg);
-	for(i=0;i<var_num;i++) {
+	for (i=0;i<var_num;i++) {
 		pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
 	}
 
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index 0d014aa815..a167848b26 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -51,73 +51,71 @@ u16 MacAddr[3];
 
 static void writeApcByte(int addr, u8 value)
 {
-    outb(addr,0x78);
-    outb(value,0x79);
+	outb(addr,0x78);
+	outb(value,0x79);
 }
 
 static u8 readApcByte(int addr)
 {
-    u8 value;
-    outb(addr,0x78);
-    value=inb(0x79);
-    return(value);
+	u8 value;
+	outb(addr,0x78);
+	value=inb(0x79);
+	return(value);
 }
 
 static void readApcMacAddr(void)
 {
-    u8 i;
+	u8 i;
 
 // enable APC in south bridge sis966 D2F0
 
-    outl(0x80001048,0xcf8);
-    outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
+	outl(0x80001048,0xcf8);
+	outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
 
-    printk(BIOS_DEBUG, "MAC addr in APC = ");
-    for (i = 0x9 ; i <=0xe ; i++)
-    {
-        printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
-    }
-    printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "MAC addr in APC = ");
+	for (i = 0x9 ; i <=0xe ; i++) {
+		printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
+	}
+	printk(BIOS_DEBUG, "\n");
 
-    /* Set APC Reload */
-    writeApcByte(0x7,readApcByte(0x7)&0xf7);
-    writeApcByte(0x7,readApcByte(0x7)|0x0a);
+	/* Set APC Reload */
+	writeApcByte(0x7,readApcByte(0x7)&0xf7);
+	writeApcByte(0x7,readApcByte(0x7)|0x0a);
 
-    /* disable APC in south bridge */
-    outl(0x80001048,0xcf8);
-    outl(inl(0xcfc)&0xffffffbf,0xcfc);
+	/* disable APC in south bridge */
+	outl(0x80001048,0xcf8);
+	outl(inl(0xcfc)&0xffffffbf,0xcfc);
 }
 
 static void set_apc(struct device *dev)
 {
-    u16 addr;
-    u16 i;
-    u8   bTmp;
-
-    /* enable APC in south bridge sis966 D2F0 */
-    outl(0x80001048,0xcf8);
-    outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
-
-    for (i = 0 ; i <3; i++)
-    {
-       addr=0x9+2*i;
-       writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
-	writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
-        // printf("%x - ",readMacAddrByte(0x59+i));
-    }
-
-    /* Set APC Reload */
-    writeApcByte(0x7,readApcByte(0x7)&0xf7);
-    writeApcByte(0x7,readApcByte(0x7)|0x0a);
-
-    /* disable APC in south bridge */
-    outl(0x80001048,0xcf8);
-    outl(inl(0xcfc)&0xffffffbf,0xcfc);
-
-    // CFG reg0x73 bit=1, tell driver MAC Address load to APC
-    bTmp = pci_read_config8(dev, 0x73);
-    bTmp|=0x1;
-    pci_write_config8(dev, 0x73, bTmp);
+	u16 addr;
+	u16 i;
+	u8   bTmp;
+
+	/* enable APC in south bridge sis966 D2F0 */
+	outl(0x80001048,0xcf8);
+	outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
+
+	for (i = 0 ; i <3; i++) {
+		addr=0x9+2*i;
+		writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
+		writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
+		// printf("%x - ",readMacAddrByte(0x59+i));
+	}
+
+	/* Set APC Reload */
+	writeApcByte(0x7,readApcByte(0x7)&0xf7);
+	writeApcByte(0x7,readApcByte(0x7)|0x0a);
+
+	/* disable APC in south bridge */
+	outl(0x80001048,0xcf8);
+	outl(inl(0xcfc)&0xffffffbf,0xcfc);
+
+	// CFG reg0x73 bit=1, tell driver MAC Address load to APC
+	bTmp = pci_read_config8(dev, 0x73);
+	bTmp|=0x1;
+	pci_write_config8(dev, 0x73, bTmp);
 }
 
 /**
@@ -131,100 +129,88 @@ static void set_apc(struct device *dev)
 #define LoopNum 200
 static  unsigned long ReadEEprom( struct device *dev,  u8 *base,  u32 Reg)
 {
-    u32 	data;
-    u32 	i;
-    u32 	ulValue;
+	u32 	data;
+	u32 	i;
+	u32 	ulValue;
 
+	ulValue = (0x80 | (0x2 << 8) | (Reg << 10));  //BIT_7
 
-    ulValue = (0x80 | (0x2 << 8) | (Reg << 10));  //BIT_7
+	write32(base + 0x3c, ulValue);
 
-    write32(base + 0x3c, ulValue);
+	mdelay(10);
 
-    mdelay(10);
+	for (i=0 ; i <= LoopNum; i++) {
+		ulValue=read32(base + 0x3c);
 
-    for (i=0 ; i <= LoopNum; i++)
-    {
-	ulValue=read32(base + 0x3c);
+		if (!(ulValue & 0x0080)) //BIT_7
+		break;
 
-        if (!(ulValue & 0x0080)) //BIT_7
-            break;
-
-        mdelay(100);
-    }
+		mdelay(100);
+	}
 
-    mdelay(50);
+	mdelay(50);
 
-    if (i==LoopNum)   data=0x10000;
-    else{
-	ulValue=read32(base + 0x3c);
-    	data = ((ulValue & 0xffff0000) >> 16);
-    }
+	if (i==LoopNum)   data=0x10000;
+	else {
+		ulValue=read32(base + 0x3c);
+		data = ((ulValue & 0xffff0000) >> 16);
+	}
 
-    return data;
+	return data;
 }
 
 static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
 {
-    u32   ulValue;
-    u32   Read_Cmd;
-    u16   usData;
-
-
-
-	   Read_Cmd = ((phy_reg << 11) |
-                       (phy_addr << 6) |
-     		       SMI_READ |
-     		       SMI_REQUEST);
-
-           // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
-	   write32(base + 0x44, Read_Cmd);
-
-           // Polling SMI_REQ bit to be deasserted indicated read command completed
-           do
-           {
-	       // Wait 20 usec before checking status
-		   mdelay(20);
-		   ulValue = read32(base + 0x44);
-           } while((ulValue & SMI_REQUEST) != 0);
-            //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
-           usData=(ulValue>>16);
-
-
+	u32   ulValue;
+	u32   Read_Cmd;
+	u16   usData;
+
+	Read_Cmd = ((phy_reg << 11) |
+			(phy_addr << 6) |
+			SMI_READ |
+			SMI_REQUEST);
+
+	// SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
+	write32(base + 0x44, Read_Cmd);
+
+	// Polling SMI_REQ bit to be deasserted indicated read command completed
+	do {
+		// Wait 20 usec before checking status
+		mdelay(20);
+		ulValue = read32(base + 0x44);
+	} while ((ulValue & SMI_REQUEST) != 0);
+	//printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
+	usData=(ulValue>>16);
 
 	return usData;
-
 }
 
 // Detect a valid PHY
 // If there exist a valid PHY then return TRUE, else return FALSE
 static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
 {
-    int	              bFoundPhy = FALSE;
-    u16		usData;
-    int		       PhyAddress = 0;
+	int	              bFoundPhy = FALSE;
+	u16		usData;
+	int		       PhyAddress = 0;
 
 
-        // Scan all PHY address(0 ~ 31) to find a valid PHY
-        for (PhyAddress = 0; PhyAddress < 32; PhyAddress++)
-        {
+	// Scan all PHY address(0 ~ 31) to find a valid PHY
+	for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) {
 		usData=phy_read(base,PhyAddress,StatusReg);  // Status register is a PHY's register(offset 01h)
 
-           // Found a valid PHY
-
-           if ((usData != 0x0) && (usData != 0xffff))
-           {
-               bFoundPhy = TRUE;
-               break;
-           }
-        }
+		// Found a valid PHY
 
+		if ((usData != 0x0) && (usData != 0xffff)) {
+			bFoundPhy = TRUE;
+			break;
+		}
+	}
 
-	if (!bFoundPhy)
-	{
-	    printk(BIOS_DEBUG, "PHY not found !!!!\n");
+	if (!bFoundPhy) {
+		printk(BIOS_DEBUG, "PHY not found !!!!\n");
 	}
 
-       *PhyAddr=PhyAddress;
+	*PhyAddr=PhyAddress;
 
 	return bFoundPhy;
 }
@@ -232,59 +218,55 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
 
 static void nic_init(struct device *dev)
 {
-        int val;
-        u16 PhyAddr;
-        u8 *base;
-        struct resource *res;
+	int val;
+	u16 PhyAddr;
+	u8 *base;
+	struct resource *res;
 
-        printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
+	printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
 
 //-------------- enable NIC (SiS19x) -------------------------
 {
-        u8  temp8;
-        int i=0;
-        while(SiS_SiS191_init[i][0] != 0)
-	{
-                temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
-                temp8 &= SiS_SiS191_init[i][1];
-                temp8 |= SiS_SiS191_init[i][2];
-                pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
-                i++;
+	u8  temp8;
+	int i=0;
+	while (SiS_SiS191_init[i][0] != 0) {
+		temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
+		temp8 &= SiS_SiS191_init[i][1];
+		temp8 |= SiS_SiS191_init[i][2];
+		pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
+		i++;
 	};
 }
 //-----------------------------------------------------------
 
 {
-        unsigned long  i;
-        unsigned long ulValue;
+	unsigned long  i;
+	unsigned long ulValue;
 
 	res = find_resource(dev, 0x10);
 
-	if (!res)
-	{
+	if (!res) {
 		printk(BIOS_DEBUG, "NIC Cannot find resource..\n");
 		return;
 	}
 	base = res2mmio(res, 0, 0);
-        printk(BIOS_DEBUG, "NIC base address %p\n",base);
+	printk(BIOS_DEBUG, "NIC base address %p\n",base);
 
-	if (!(val=phy_detect(base,&PhyAddr)))
-	{
-	       printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
+	if (!(val=phy_detect(base,&PhyAddr))) {
+		printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
 		return;
 	}
 
-        ulValue=read32(base + 0x38L);   //  check EEPROM existing
+	ulValue=read32(base + 0x38L);   //  check EEPROM existing
 
-        if ((ulValue & 0x0002))
-        {
+	if ((ulValue & 0x0002)) {
 
-          //	read MAC address from EEPROM at first
+	  //	read MAC address from EEPROM at first
 
-          //	if that is valid we will use that
+	  //	if that is valid we will use that
 
 			printk(BIOS_DEBUG, "EEPROM contents %lx\n",ReadEEprom( dev,  base,  0LL));
-			for(i=0;i<3;i++) {
+			for (i=0;i<3;i++) {
 				//status = smbus_read_byte(dev_eeprom, i);
 				ulValue=ReadEEprom( dev,  base,  i+3L);
 				if (ulValue ==0x10000) break;  // error
@@ -292,31 +274,31 @@ static void nic_init(struct device *dev)
 				MacAddr[i] =ulValue & 0xFFFF;
 
 			}
-        }else{
-                 // read MAC address from firmware
-		 printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue);
-		 MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
-		 MacAddr[1]=read16((u16 *)0xffffffc2);
-		 MacAddr[2]=read16((u16 *)0xffffffc4);
-        }
+	} else {
+		// read MAC address from firmware
+		printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue);
+		MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
+		MacAddr[1]=read16((u16 *)0xffffffc2);
+		MacAddr[2]=read16((u16 *)0xffffffc4);
+	}
 
-        set_apc(dev);
+	set_apc(dev);
 
-        readApcMacAddr();
+	readApcMacAddr();
 
 #if DEBUG_NIC
 {
-        int i;
+	int i;
 
-        printk(BIOS_DEBUG, "****** NIC PCI config ******");
-        printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
+	printk(BIOS_DEBUG, "****** NIC PCI config ******");
+	printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
 
-        for (i=0;i<0xff;i+=4){
-                if ((i%16)==0)
-                        printk(BIOS_DEBUG, "\n%02x: ", i);
-                printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
-        }
-        printk(BIOS_DEBUG, "\n");
+	for (i=0;i<0xff;i+=4) {
+		if ((i%16)==0)
+			printk(BIOS_DEBUG, "\n%02x: ", i);
+		printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
+	}
+	printk(BIOS_DEBUG, "\n");
 }
 
 
diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c
index eb69ab074a..3f114a0148 100644
--- a/src/southbridge/sis/sis966/sata.c
+++ b/src/southbridge/sis/sis966/sata.c
@@ -109,22 +109,19 @@ static void sata_init(struct device *dev)
 {
 	struct southbridge_sis_sis966_config *conf;
 
-
-
 	conf = dev->chip_info;
-        printk(BIOS_DEBUG, "SATA_INIT:---------->\n");
+	printk(BIOS_DEBUG, "SATA_INIT:---------->\n");
 
 //-------------- enable IDE (SiS1183) -------------------------
 {
-        uint8_t  temp8;
-        int i=0;
-	while(SiS_SiS1183_init[i][0] != 0)
-	{
-                temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
-                temp8 &= SiS_SiS1183_init[i][1];
-                temp8 |= SiS_SiS1183_init[i][2];
-                pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
-                i++;
+	uint8_t  temp8;
+	int i=0;
+	while (SiS_SiS1183_init[i][0] != 0) {
+		temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
+		temp8 &= SiS_SiS1183_init[i][1];
+		temp8 |= SiS_SiS1183_init[i][2];
+		pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
+		i++;
 	};
 }
 //-----------------------------------------------------------
@@ -133,33 +130,33 @@ static void sata_init(struct device *dev)
 uint32_t i,j;
 uint32_t temp32;
 
-for (i=0;i<10;i++){
-   temp32=0;
-   temp32= pci_read_config32(dev, 0xC0);
-   for ( j=0;j<0xFFFF;j++);
-   printk(BIOS_DEBUG, "status= %x\n",temp32);
-   if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break;
+for (i=0;i<10;i++) {
+	temp32=0;
+	temp32= pci_read_config32(dev, 0xC0);
+	for ( j=0;j<0xFFFF;j++);
+		printk(BIOS_DEBUG, "status= %x\n",temp32);
+		if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break;
 }
 
 }
 
 #if DEBUG_SATA
 {
-        int i;
+	int i;
 
-        printk(BIOS_DEBUG, "****** SATA PCI config ******");
-        printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
+	printk(BIOS_DEBUG, "****** SATA PCI config ******");
+	printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
 
-        for (i=0;i<0xff;i+=4){
-                if ((i%16)==0)
-                        printk(BIOS_DEBUG, "\n%02x: ", i);
-                printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
-        }
-        printk(BIOS_DEBUG, "\n");
+	for (i=0;i<0xff;i+=4) {
+		if ((i%16)==0)
+			printk(BIOS_DEBUG, "\n%02x: ", i);
+		printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
+	}
+	printk(BIOS_DEBUG, "\n");
 }
 #endif
 
-        printk(BIOS_DEBUG, "SATA_INIT:<----------\n");
+	printk(BIOS_DEBUG, "SATA_INIT:<----------\n");
 
 }
 
diff --git a/src/southbridge/sis/sis966/sis966.c b/src/southbridge/sis/sis966/sis966.c
index 6ac15db414..57d649857e 100644
--- a/src/southbridge/sis/sis966/sis966.c
+++ b/src/southbridge/sis/sis966/sis966.c
@@ -70,7 +70,7 @@ void sis966_enable(device_t dev)
 	conf = dev->chip_info;
 	int i;
 
-	if(dev->device==0x0000) {
+	if (dev->device==0x0000) {
 		reg = pci_read_config32(dev, PCI_VENDOR_ID);
 		deviceid = (reg >> 16) & 0xffff;
 		vendorid = reg & 0xffff;
@@ -92,9 +92,9 @@ void sis966_enable(device_t dev)
 		case PCI_DEVICE_ID_SIS_SIS966_NIC:
 			devfn -= (7<<3);
 			index = 10;
-			for(i=0;i<2;i++) {
+			for (i=0;i<2;i++) {
 				lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
-				if(!lpc_dev) continue;
+				if (!lpc_dev) continue;
 				index -= i;
 				devfn -= (i<<3);
 				break;
@@ -112,7 +112,7 @@ void sis966_enable(device_t dev)
 			devfn -= (4<<3);
 			index = 22;
 			i = (dev->path.pci.devfn) & 7;
-			if(i>0) {
+			if (i>0) {
 				index -= (i+3);
 			}
 			break;
@@ -124,14 +124,14 @@ void sis966_enable(device_t dev)
 			index = 0;
 	}
 
-	if(!lpc_dev)
+	if (!lpc_dev)
 		lpc_dev = find_lpc_dev(dev, devfn);
 
 	if ( !lpc_dev )	return;
 
-	if(index2!=0) {
+	if (index2!=0) {
 		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
-		if(!sm_dev) return;
+		if (!sm_dev) return;
 
 		if ( sm_dev ) {
 			reg_old = reg =  pci_read_config32(sm_dev, 0xe4);
@@ -165,9 +165,9 @@ void sis966_enable(device_t dev)
 
 	}
 
-	if( index == 16) {
+	if ( index == 16) {
 		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
-		if(!sm_dev) return;
+		if (!sm_dev) return;
 
 		final_reg = pci_read_config32(sm_dev, 0xe8);
 		final_reg &= ~0x0057cf00;
@@ -184,9 +184,9 @@ void sis966_enable(device_t dev)
 		 */
 	}
 
-	if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
+	if (index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
 		sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
-		if(!sm_dev) return;
+		if (!sm_dev) return;
 		reg_old = pci_read_config32(sm_dev, 0xe8);
 		if (final_reg != reg_old) {
 			pci_write_config32(sm_dev, 0xe8, final_reg);
diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c
index 64398e2661..3f4f98d3e3 100644
--- a/src/southbridge/sis/sis966/usb.c
+++ b/src/southbridge/sis/sis966/usb.c
@@ -51,39 +51,39 @@ uint8_t	SiS_SiS7001_init[16][3]={
 
 static void usb_init(struct device *dev)
 {
-        printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");
+	printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");
 
 //-------------- enable USB1.1 (SiS7001) -------------------------
 {
-        uint8_t  temp8;
-        int i=0;
+	uint8_t  temp8;
+	int i=0;
 
-	 while(SiS_SiS7001_init[i][0] != 0)
-	 {				temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
-					temp8 &= SiS_SiS7001_init[i][1];
-					temp8 |= SiS_SiS7001_init[i][2];
-					pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8);
-					i++;
-	 };
+	while (SiS_SiS7001_init[i][0] != 0) {
+		temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
+		temp8 &= SiS_SiS7001_init[i][1];
+		temp8 |= SiS_SiS7001_init[i][2];
+		pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8);
+		i++;
+	};
 }
 //-----------------------------------------------------------
 
 #if DEBUG_USB
 {
-        int i;
+	int i;
 
-        printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
-        printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
+	printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
+	printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
 
-        for (i=0;i<0xff;i+=4){
-                if ((i%16)==0)
-                        printk(BIOS_DEBUG, "\n%02x: ", i);
-                printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
-        }
-        printk(BIOS_DEBUG, "\n");
+	for (i=0;i<0xff;i+=4) {
+		if ((i%16)==0)
+			printk(BIOS_DEBUG, "\n%02x: ", i);
+		printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
+	}
+	printk(BIOS_DEBUG, "\n");
 }
 #endif
-        printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n");
+	printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n");
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c
index 8c3472335a..79e7d09232 100644
--- a/src/southbridge/sis/sis966/usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
@@ -62,46 +62,45 @@ static const u8 SiS_SiS7002_init[22][3]={
 
 static void usb2_init(struct device *dev)
 {
-        u8 *base;
-        struct resource *res;
-        int i;
-        u8  temp8;
+	u8 *base;
+	struct resource *res;
+	int i;
+	u8  temp8;
 
-        printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n");
+	printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n");
 
 	//-------------- enable USB2.0 (SiS7002) ----------------------
 
 	i = 0;
-        while (SiS_SiS7002_init[i][0] != 0)
-        {
-                temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
-                temp8 &= SiS_SiS7002_init[i][1];
-                temp8 |= SiS_SiS7002_init[i][2];
-                pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
-                i++;
-        };
-
-        res = find_resource(dev, 0x10);
-        if (!res)
-                return;
-
-        base = res2mmio(res, 0, 0);
-        printk(BIOS_DEBUG, "base = 0x%p\n", base);
-        write32(base + 0x20, 0x2);
+	while (SiS_SiS7002_init[i][0] != 0) {
+		temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
+		temp8 &= SiS_SiS7002_init[i][1];
+		temp8 |= SiS_SiS7002_init[i][2];
+		pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
+		i++;
+	};
+
+	res = find_resource(dev, 0x10);
+	if (!res)
+		return;
+
+	base = res2mmio(res, 0, 0);
+	printk(BIOS_DEBUG, "base = 0x%p\n", base);
+	write32(base + 0x20, 0x2);
 	//-------------------------------------------------------------
 
 #if DEBUG_USB2
-        printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******");
-        printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
-
-        for (i=0;i<0xff;i+=4){
-                if ((i%16)==0)
-                        printk(BIOS_DEBUG, "\n%02x: ", i);
-                printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
-        }
-        printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******");
+	printk(BIOS_DEBUG, "\n    03020100  07060504  0B0A0908  0F0E0D0C");
+
+	for (i=0;i<0xff;i+=4) {
+		if ((i%16)==0)
+			printk(BIOS_DEBUG, "\n%02x: ", i);
+		printk(BIOS_DEBUG, "%08x  ", pci_read_config32(dev,i));
+	}
+	printk(BIOS_DEBUG, "\n");
 #endif
-        printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n");
+	printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n");
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)