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authorLee Leahy <leroy.p.leahy@intel.com>2017-06-27 09:28:35 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-06-27 21:55:49 +0000
commitf968a4c970e2806dcf15630dc71d2ebcf54736f1 (patch)
tree05aff154cec809e803b7b4608a3b4de21890abf7 /src/southbridge/sis/sis966
parentf138320f9e4ac5b3650f2044c0136bfc3f295c1e (diff)
commonlib/storage: Zero extend MMC capacity
Fix CID 1376472 detected by coverity. Zero extend the capacity instead of sign extending it. TEST=Build and run on reef Change-Id: I6aac422fb1dacb75e0cc44a94ff1f467ce9f529e Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/20392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'src/southbridge/sis/sis966')
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