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authorElyes HAOUAS <ehaouas@noos.fr>2016-08-31 19:22:16 +0200
committerMartin Roth <martinroth@google.com>2016-08-31 20:22:46 +0200
commitba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 (patch)
tree9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f /src/southbridge/sis/sis966/nic.c
parent2e4d80687dd79890c7c9edad8dbaf6e89edf2afc (diff)
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/sis/sis966/nic.c')
-rw-r--r--src/southbridge/sis/sis966/nic.c302
1 files changed, 142 insertions, 160 deletions
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index 0d014aa815..a167848b26 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -51,73 +51,71 @@ u16 MacAddr[3];
static void writeApcByte(int addr, u8 value)
{
- outb(addr,0x78);
- outb(value,0x79);
+ outb(addr,0x78);
+ outb(value,0x79);
}
static u8 readApcByte(int addr)
{
- u8 value;
- outb(addr,0x78);
- value=inb(0x79);
- return(value);
+ u8 value;
+ outb(addr,0x78);
+ value=inb(0x79);
+ return(value);
}
static void readApcMacAddr(void)
{
- u8 i;
+ u8 i;
// enable APC in south bridge sis966 D2F0
- outl(0x80001048,0xcf8);
- outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
+ outl(0x80001048,0xcf8);
+ outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
- printk(BIOS_DEBUG, "MAC addr in APC = ");
- for (i = 0x9 ; i <=0xe ; i++)
- {
- printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
- }
- printk(BIOS_DEBUG, "\n");
+ printk(BIOS_DEBUG, "MAC addr in APC = ");
+ for (i = 0x9 ; i <=0xe ; i++) {
+ printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
+ }
+ printk(BIOS_DEBUG, "\n");
- /* Set APC Reload */
- writeApcByte(0x7,readApcByte(0x7)&0xf7);
- writeApcByte(0x7,readApcByte(0x7)|0x0a);
+ /* Set APC Reload */
+ writeApcByte(0x7,readApcByte(0x7)&0xf7);
+ writeApcByte(0x7,readApcByte(0x7)|0x0a);
- /* disable APC in south bridge */
- outl(0x80001048,0xcf8);
- outl(inl(0xcfc)&0xffffffbf,0xcfc);
+ /* disable APC in south bridge */
+ outl(0x80001048,0xcf8);
+ outl(inl(0xcfc)&0xffffffbf,0xcfc);
}
static void set_apc(struct device *dev)
{
- u16 addr;
- u16 i;
- u8 bTmp;
-
- /* enable APC in south bridge sis966 D2F0 */
- outl(0x80001048,0xcf8);
- outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
-
- for (i = 0 ; i <3; i++)
- {
- addr=0x9+2*i;
- writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
- writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
- // printf("%x - ",readMacAddrByte(0x59+i));
- }
-
- /* Set APC Reload */
- writeApcByte(0x7,readApcByte(0x7)&0xf7);
- writeApcByte(0x7,readApcByte(0x7)|0x0a);
-
- /* disable APC in south bridge */
- outl(0x80001048,0xcf8);
- outl(inl(0xcfc)&0xffffffbf,0xcfc);
-
- // CFG reg0x73 bit=1, tell driver MAC Address load to APC
- bTmp = pci_read_config8(dev, 0x73);
- bTmp|=0x1;
- pci_write_config8(dev, 0x73, bTmp);
+ u16 addr;
+ u16 i;
+ u8 bTmp;
+
+ /* enable APC in south bridge sis966 D2F0 */
+ outl(0x80001048,0xcf8);
+ outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
+
+ for (i = 0 ; i <3; i++) {
+ addr=0x9+2*i;
+ writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
+ writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
+ // printf("%x - ",readMacAddrByte(0x59+i));
+ }
+
+ /* Set APC Reload */
+ writeApcByte(0x7,readApcByte(0x7)&0xf7);
+ writeApcByte(0x7,readApcByte(0x7)|0x0a);
+
+ /* disable APC in south bridge */
+ outl(0x80001048,0xcf8);
+ outl(inl(0xcfc)&0xffffffbf,0xcfc);
+
+ // CFG reg0x73 bit=1, tell driver MAC Address load to APC
+ bTmp = pci_read_config8(dev, 0x73);
+ bTmp|=0x1;
+ pci_write_config8(dev, 0x73, bTmp);
}
/**
@@ -131,100 +129,88 @@ static void set_apc(struct device *dev)
#define LoopNum 200
static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
{
- u32 data;
- u32 i;
- u32 ulValue;
+ u32 data;
+ u32 i;
+ u32 ulValue;
+ ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7
- ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7
+ write32(base + 0x3c, ulValue);
- write32(base + 0x3c, ulValue);
+ mdelay(10);
- mdelay(10);
+ for (i=0 ; i <= LoopNum; i++) {
+ ulValue=read32(base + 0x3c);
- for (i=0 ; i <= LoopNum; i++)
- {
- ulValue=read32(base + 0x3c);
+ if (!(ulValue & 0x0080)) //BIT_7
+ break;
- if (!(ulValue & 0x0080)) //BIT_7
- break;
-
- mdelay(100);
- }
+ mdelay(100);
+ }
- mdelay(50);
+ mdelay(50);
- if (i==LoopNum) data=0x10000;
- else{
- ulValue=read32(base + 0x3c);
- data = ((ulValue & 0xffff0000) >> 16);
- }
+ if (i==LoopNum) data=0x10000;
+ else {
+ ulValue=read32(base + 0x3c);
+ data = ((ulValue & 0xffff0000) >> 16);
+ }
- return data;
+ return data;
}
static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
{
- u32 ulValue;
- u32 Read_Cmd;
- u16 usData;
-
-
-
- Read_Cmd = ((phy_reg << 11) |
- (phy_addr << 6) |
- SMI_READ |
- SMI_REQUEST);
-
- // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
- write32(base + 0x44, Read_Cmd);
-
- // Polling SMI_REQ bit to be deasserted indicated read command completed
- do
- {
- // Wait 20 usec before checking status
- mdelay(20);
- ulValue = read32(base + 0x44);
- } while((ulValue & SMI_REQUEST) != 0);
- //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
- usData=(ulValue>>16);
-
-
+ u32 ulValue;
+ u32 Read_Cmd;
+ u16 usData;
+
+ Read_Cmd = ((phy_reg << 11) |
+ (phy_addr << 6) |
+ SMI_READ |
+ SMI_REQUEST);
+
+ // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
+ write32(base + 0x44, Read_Cmd);
+
+ // Polling SMI_REQ bit to be deasserted indicated read command completed
+ do {
+ // Wait 20 usec before checking status
+ mdelay(20);
+ ulValue = read32(base + 0x44);
+ } while ((ulValue & SMI_REQUEST) != 0);
+ //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
+ usData=(ulValue>>16);
return usData;
-
}
// Detect a valid PHY
// If there exist a valid PHY then return TRUE, else return FALSE
static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
{
- int bFoundPhy = FALSE;
- u16 usData;
- int PhyAddress = 0;
+ int bFoundPhy = FALSE;
+ u16 usData;
+ int PhyAddress = 0;
- // Scan all PHY address(0 ~ 31) to find a valid PHY
- for (PhyAddress = 0; PhyAddress < 32; PhyAddress++)
- {
+ // Scan all PHY address(0 ~ 31) to find a valid PHY
+ for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) {
usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h)
- // Found a valid PHY
-
- if ((usData != 0x0) && (usData != 0xffff))
- {
- bFoundPhy = TRUE;
- break;
- }
- }
+ // Found a valid PHY
+ if ((usData != 0x0) && (usData != 0xffff)) {
+ bFoundPhy = TRUE;
+ break;
+ }
+ }
- if (!bFoundPhy)
- {
- printk(BIOS_DEBUG, "PHY not found !!!!\n");
+ if (!bFoundPhy) {
+ printk(BIOS_DEBUG, "PHY not found !!!!\n");
}
- *PhyAddr=PhyAddress;
+ *PhyAddr=PhyAddress;
return bFoundPhy;
}
@@ -232,59 +218,55 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
static void nic_init(struct device *dev)
{
- int val;
- u16 PhyAddr;
- u8 *base;
- struct resource *res;
+ int val;
+ u16 PhyAddr;
+ u8 *base;
+ struct resource *res;
- printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
+ printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
//-------------- enable NIC (SiS19x) -------------------------
{
- u8 temp8;
- int i=0;
- while(SiS_SiS191_init[i][0] != 0)
- {
- temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
- temp8 &= SiS_SiS191_init[i][1];
- temp8 |= SiS_SiS191_init[i][2];
- pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
- i++;
+ u8 temp8;
+ int i=0;
+ while (SiS_SiS191_init[i][0] != 0) {
+ temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
+ temp8 &= SiS_SiS191_init[i][1];
+ temp8 |= SiS_SiS191_init[i][2];
+ pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
+ i++;
};
}
//-----------------------------------------------------------
{
- unsigned long i;
- unsigned long ulValue;
+ unsigned long i;
+ unsigned long ulValue;
res = find_resource(dev, 0x10);
- if (!res)
- {
+ if (!res) {
printk(BIOS_DEBUG, "NIC Cannot find resource..\n");
return;
}
base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "NIC base address %p\n",base);
+ printk(BIOS_DEBUG, "NIC base address %p\n",base);
- if (!(val=phy_detect(base,&PhyAddr)))
- {
- printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
+ if (!(val=phy_detect(base,&PhyAddr))) {
+ printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
return;
}
- ulValue=read32(base + 0x38L); // check EEPROM existing
+ ulValue=read32(base + 0x38L); // check EEPROM existing
- if ((ulValue & 0x0002))
- {
+ if ((ulValue & 0x0002)) {
- // read MAC address from EEPROM at first
+ // read MAC address from EEPROM at first
- // if that is valid we will use that
+ // if that is valid we will use that
printk(BIOS_DEBUG, "EEPROM contents %lx\n",ReadEEprom( dev, base, 0LL));
- for(i=0;i<3;i++) {
+ for (i=0;i<3;i++) {
//status = smbus_read_byte(dev_eeprom, i);
ulValue=ReadEEprom( dev, base, i+3L);
if (ulValue ==0x10000) break; // error
@@ -292,31 +274,31 @@ static void nic_init(struct device *dev)
MacAddr[i] =ulValue & 0xFFFF;
}
- }else{
- // read MAC address from firmware
- printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue);
- MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
- MacAddr[1]=read16((u16 *)0xffffffc2);
- MacAddr[2]=read16((u16 *)0xffffffc4);
- }
+ } else {
+ // read MAC address from firmware
+ printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue);
+ MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
+ MacAddr[1]=read16((u16 *)0xffffffc2);
+ MacAddr[2]=read16((u16 *)0xffffffc4);
+ }
- set_apc(dev);
+ set_apc(dev);
- readApcMacAddr();
+ readApcMacAddr();
#if DEBUG_NIC
{
- int i;
+ int i;
- printk(BIOS_DEBUG, "****** NIC PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** NIC PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for (i=0;i<0xff;i+=4){
- if ((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ for (i=0;i<0xff;i+=4) {
+ if ((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}