Remove southbridges after K8 board removals

Change-Id: Ib6935c026e2302b037fc82be64163f10bf775751
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 0 insertions, 45 deletions

diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
deleted file mode 100644
index 6be115e3e5..0000000000
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
- * Copyright (C) 2006,2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* TODO: Check whether this actually works (might be copy-paste leftover). */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <device/pci_ehci.h>
-#include <device/pci_def.h>
-#include "sis966.h"
-
-pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
-{
-	return PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
-}
-
-void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
-{
-	u32 dword;
-
-	/* Write the port number to 0x74[15:12]. */
-	dword = pci_read_config32(dev, 0x74);
-	dword &= ~(0xf << 12);
-	dword |= (port << 12);
-	pci_write_config32(dev, 0x74, dword);
-}