diff options
| author | Yu-Ping Wu <yupingso@chromium.org> | 2021-01-21 14:51:50 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-01 09:04:48 +0000 |
| commit | 39a84879f5c2c220e91cd7e69587d76cb3438cc0 (patch) | |
| tree | 1a643cc821633e3361851b9175af68828487b60c /src/southbridge/ricoh | |
| parent | 3b7983a044d2fac04f2c59685774987d31e45083 (diff) | |
soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE size
From the output of 'objdump -x dram.elf', the DRAM blob needs 222K
memory, but currently only 208K is reserved for it. Since MT8192 has 1MB
SRAM L2C, increase SRAM_L2C_END to 0x00300000, and reorganize regions in
SRAM_L2C to have larger DRAM_INIT_CODE (256K). The size of
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE is also increased to 252K.
BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Asurada booted successfully
BRANCH=none
Cq-Depend: chrome-internal:3568265
Change-Id: I062f00739b72cf6b1bb7ac3318b91721fbe226cc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/southbridge/ricoh')
0 files changed, 0 insertions, 0 deletions