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| author | Xi Chen <xixi.chen@mediatek.com> | 2022-07-28 13:45:18 +0800 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-27 15:54:53 +0000 |
| commit | bcaa87d603441b74b7f1cf504bf7cb03aa8dafc9 (patch) | |
| tree | 3d1452b26627692fb833fe6d128d9af3aec972e2 /src/southbridge/ricoh | |
| parent | 22ce1e80af945d0d24ce70b0bc7761e0df6512b0 (diff) | |
mb/google/geralt: Fully calibrate DRAM
Initialize and calibrate DRAM in romstage.
DRAM full calibration logs:
dram_init: dram init end (result: 0)
DRAM-K: Full calibration passed in 50176 msecs
TEST=Full calibration pass.
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I31f5693ffe4a1e30defbc8a96dc128de03d6b7e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66278
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/ricoh')
0 files changed, 0 insertions, 0 deletions