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authorHung-Te Lin <hungte@chromium.org>2019-09-26 12:33:25 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-10-04 16:25:56 +0000
commitb763b37411f82c8df091cc4f15925db9daa5ce2e (patch)
tree4b033ffa0ecabeeb759f4492737fe41a30e17d0c /src/southbridge/ricoh/rl5c476
parentb3d597b1dddcacbae58115273a9b85c971eb830a (diff)
mb/google/kukui: Extend FMAP to 8MB layout
The SPI flash component requirement for Kukui family is 8M so we should update FMAP for that: - Add more comments for alignment and size recommendation. - Enlarge RO to 4M, and RW_SECTION_{A,B} both ~1.5M. - BOOTBLOCK: 32K->128K, aligned with other ARM boards. - Preserve RW_DDR_TRAINING for new calibration. - Reorder the sections for better alignment. - RW_MISC to contain RW sections that should be merged when creating AU image. BUG=b:134624821 TEST=Built Kukui image and boots. dump_fmap -h image-kukui.bin: # name start end size RW_LEGACY 00700000 00800000 00100000 RW_SHARED 006f7000 00700000 00009000 RW_UNUSED 006f8000 00700000 00008000 SHARED_DATA 006f7000 006f8000 00001000 RW_SECTION_B 00580000 006f7000 00177000 RW_FWID_B 006f6f00 006f7000 00000100 FW_MAIN_B 00582000 006f6f00 00174f00 VBLOCK_B 00580000 00582000 00002000 RW_MISC 00577000 00580000 00009000 RW_ELOG 0057f000 00580000 00001000 RW_DDR_TRAINING 0057d000 0057f000 00002000 RW_NVRAM 0057b000 0057d000 00002000 RW_VPD 00577000 0057b000 00004000 RW_SECTION_A 00400000 00577000 00177000 RW_FWID_A 00576f00 00577000 00000100 FW_MAIN_A 00402000 00576f00 00174f00 VBLOCK_A 00400000 00402000 00002000 WP_RO 00000000 00400000 00400000 RO_VPD 003f8000 00400000 00008000 RO_SECTION 00000000 003f8000 003f8000 RO_FRID 003f7f00 003f8000 00000100 GBB 003f5000 003f7f00 00002f00 COREBOOT 00021000 003f5000 003d4000 FMAP 00020000 00021000 00001000 BOOTBLOCK 00000000 00020000 00020000 Change-Id: Id342d57dc95c6197d05b8a265742a2866c35ae09 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/southbridge/ricoh/rl5c476')
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