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authorFelix Held <felix-coreboot@felixheld.de>2021-05-12 01:23:50 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-05-13 00:58:17 +0000
commitdd882f3812c5fe2fa3f709ed5e61938e723ba51d (patch)
tree989b9f6a57441c4e60a291d09bf5f0675f1c53e0 /src/southbridge/ricoh/rl5c476
parent5c3b05ecf4dbb89da3dd7bc514875b53e3a8ce1c (diff)
soc/amd/cezanne/root_complex: generate DPTC ACPI method
This adds support for convertible devices to support different maximum power and thermal configurations. The dynamic power and thermal configuration (DPTC) via ACPI ALIB calls allows to change the parameters during runtime. This code contains the assumption that \_SB.PCI0.LPCB.EC0.TBMD exists when ACPI code calls the DPTC method. At the moment only chromeec declares EC0.TBMD, but it's also the only code that calls the DPTC method. The definition of DPTC_INPUTS isn't moved to the common code directory, since it's currently unsure if we might need to configure more than those 4 parameters for Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibdfc056cb325a32d87505dd93e01c9af81dfd6c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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