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authorRonald G. Minnich <rminnich@gmail.com>2005-11-22 00:07:02 +0000
committerRonald G. Minnich <rminnich@gmail.com>2005-11-22 00:07:02 +0000
commit43225bc8042b32d52b31c788daee1e42bd1fa28e (patch)
tree951e0acc732af7483565e4b0d5d42d1c849e2562 /src/southbridge/ricoh/rl5c476/chip.h
parent86cbd33837207e06a9ae41efe65ac2401e885c4b (diff)
EPIA-M fixup
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/ricoh/rl5c476/chip.h')
-rw-r--r--src/southbridge/ricoh/rl5c476/chip.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/ricoh/rl5c476/chip.h b/src/southbridge/ricoh/rl5c476/chip.h
index 5d7a2e3ab6..c4cd9d7997 100644
--- a/src/southbridge/ricoh/rl5c476/chip.h
+++ b/src/southbridge/ricoh/rl5c476/chip.h
@@ -1,10 +1,11 @@
#ifndef _SOUTHBRIDGE_RICOH_RL5C476
#define _SOUTHBRIDGE_RICOH_RL5C476
-extern struct chip_operations southbridge_ricoh_rl5c476_control;
+extern struct chip_operations southbridge_ricoh_rl5c476_ops;
struct southbridge_ricoh_rl5c476_config {
- int num;
+ int enable_cf;
+
};
#endif /* _SOUTHBRIDGE_RL5C476 */