diff options
| author | Andrew Chew <achew@nvidia.com> | 2014-02-10 16:33:54 -0800 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-11-12 20:14:57 +0100 |
| commit | c38c6f7211cb425afd97956b8e600366df608331 (patch) | |
| tree | 72286e91ac6774219a2db132f9d7ca33f2da5682 /src/southbridge/rdc | |
| parent | 1ecbc8cf566b7a9b68c219f588d568c791d4a899 (diff) | |
tegra124: Enable PWM clock, and set up PWM1 pin
Configure pin H1 for PWM1, and enable the PWM clock.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
Original-Change-Id: I2f91ebd4666bd227686c08cedf3c1aa7abbe8215
Original-Signed-off-by: Andrew Chew <achew@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185770
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 069636d9299f64dd64466d45d2297593b37df4f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic41515842fb883f44f228c77b4cd266e16124d99
Reviewed-on: http://review.coreboot.org/7400
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/rdc')
0 files changed, 0 insertions, 0 deletions