My old mcp55 azalia fix from May 2010. Was never checked in.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 298 insertions, 270 deletions

diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc
index c7e7e5168e..06bee2081d 100644
--- a/src/southbridge/nvidia/mcp55/Makefile.inc
+++ b/src/southbridge/nvidia/mcp55/Makefile.inc
@@ -1,5 +1,5 @@
 driver-y += mcp55.o
-driver-y += mcp55_aza.o
+driver-y += mcp55_azalia.o
 driver-y += mcp55_ht.o
 driver-y += mcp55_ide.o
 driver-y += mcp55_lpc.o
diff --git a/src/southbridge/nvidia/mcp55/mcp55_aza.c b/src/southbridge/nvidia/mcp55/mcp55_aza.c
deleted file mode 100644
index ca002b7eb2..0000000000
--- a/src/southbridge/nvidia/mcp55/mcp55_aza.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
- * Copyright (C) 2006,2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <arch/io.h>
-#include <delay.h>
-#include "mcp55.h"
-
-static int set_bits(u32 port, u32 mask, u32 val)
-{
-	u32 dword;
-	int count;
-
-	val &= mask;
-	dword = read32(port);
-	dword &= ~mask;
-	dword |= val;
-	write32(port, dword);
-
-	count = 50;
-	do {
-		dword = read32(port);
-		dword &= mask;
-		udelay(100);
-	} while ((dword != val) && --count);
-
-	if(!count) return -1;
-
-	udelay(540);
-	return 0;
-
-}
-
-static int codec_detect(u32 base)
-{
-	u32 dword;
-
-	/* 1 */
-	set_bits(base + 0x08, 1, 1);
-
-	/* 2 */
-	dword = read32(base + 0x0e);
-	dword |= 7;
-	write32(base + 0x0e, dword);
-
-	/* 3 */
-	set_bits(base + 0x08, 1, 0);
-
-	/* 4 */
-	set_bits(base + 0x08, 1, 1);
-
-	/* 5 */
-	dword = read32(base + 0xe);
-	dword &= 7;
-
-	/* 6 */
-	if(!dword) {
-		set_bits(base + 0x08, 1, 0);
-		printk(BIOS_DEBUG, "No codec!\n");
-		return 0;
-	}
-	return dword;
-
-}
-
-/* FIXME this should go to the mainboard code */
-static u32 verb_data[] = {
-#if 0
-	0x00172001,
-	0x001721e6,
-	0x00172200,
-	0x00172300,
-#endif
-
-	0x01471c10,
-	0x01471d44,
-	0x01471e01,
-	0x01471f01,
-//1
-	0x01571c12,
-	0x01571d14,
-	0x01571e01,
-	0x01571f01,
-//2
-	0x01671c11,
-	0x01671d60,
-	0x01671e01,
-	0x01671f01,
-//3
-	0x01771c14,
-	0x01771d20,
-	0x01771e01,
-	0x01771f01,
-//4
-	0x01871c30,
-	0x01871d9c,
-	0x01871ea1,
-	0x01871f01,
-//5
-	0x01971c40,
-	0x01971d9c,
-	0x01971ea1,
-	0x01971f02,
-//6
-	0x01a71c31,
-	0x01a71d34,
-	0x01a71e81,
-	0x01a71f01,
-//7
-	0x01b71c1f,
-	0x01b71d44,
-	0x01b71e21,
-	0x01b71f02,
-//8
-	0x01c71cf0,
-	0x01c71d11,
-	0x01c71e11,
-	0x01c71f41,
-//9
-	0x01d71c3e,
-	0x01d71d01,
-	0x01d71e83,
-	0x01d71f99,
-//10
-	0x01e71c20,
-	0x01e71d41,
-	0x01e71e45,
-	0x01e71f01,
-//11
-	0x01f71c50,
-	0x01f71d91,
-	0x01f71ec5,
-	0x01f71f01,
-};
-
-static unsigned find_verb(u32 viddid, u32 **verb)
-{
-	if(viddid != 0x10ec0880) return 0;
-	*verb =  (u32 *)verb_data;
-	return sizeof(verb_data)/sizeof(u32);
-}
-
-
-static void codec_init(u32 base, int addr)
-{
-	u32 dword;
-	u32 *verb;
-	unsigned verb_size;
-	int i;
-
-	/* 1 */
-	do {
-		dword = read32(base + 0x68);
-	} while (dword & 1);
-
-	dword = (addr<<28) | 0x000f0000;
-	write32(base + 0x60, dword);
-
-	do {
-		dword = read32(base + 0x68);
-	} while ((dword & 3)!=2);
-
-	dword = read32(base + 0x64);
-
-	/* 2 */
-	printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
-	verb_size = find_verb(dword, &verb);
-
-	if(!verb_size) {
-		printk(BIOS_DEBUG, "No verb!\n");
-		return;
-	}
-
-	printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
-	/* 3 */
-	for(i=0; i<verb_size; i++) {
-		do {
-			dword = read32(base + 0x68);
-		} while (dword & 1);
-
-		write32(base + 0x60, verb[i]);
-
-		do {
-			dword = read32(base + 0x68);
-		} while ((dword & 3) != 2);
-	}
-	printk(BIOS_DEBUG, "verb loaded!\n");
-}
-
-static void codecs_init(u32 base, u32 codec_mask)
-{
-	int i;
-	for(i=2; i>=0; i--) {
-		if( codec_mask & (1<<i) )
-			codec_init(base, i);
-	}
-}
-
-static void aza_init(struct device *dev)
-{
-	u32 base;
-	struct resource *res;
-	u32 codec_mask;
-
-	res = find_resource(dev, 0x10);
-	if(!res)
-		return;
-
-	base = res->base;
-	printk(BIOS_DEBUG, "base = 0x%08x\n", base);
-
-	codec_mask = codec_detect(base);
-
-	if(codec_mask) {
-		printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
-		codecs_init(base, codec_mask);
-	}
-}
-
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
-	pci_write_config32(dev, 0x40,
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations lops_pci = {
-	.set_subsystem	= lpci_set_subsystem,
-};
-
-static struct device_operations aza_audio_ops  = {
-	.read_resources	= pci_dev_read_resources,
-	.set_resources	= pci_dev_set_resources,
-	.enable_resources	= pci_dev_enable_resources,
-//	.enable		= mcp55_enable,
-	.init		= aza_init,
-	.scan_bus	= 0,
-	.ops_pci	= &lops_pci,
-};
-
-static const struct pci_driver azaaudio_driver __pci_driver = {
-	.ops	= &aza_audio_ops,
-	.vendor	= PCI_VENDOR_ID_NVIDIA,
-	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_AZA,
-};
-
diff --git a/src/southbridge/nvidia/mcp55/mcp55_azalia.c b/src/southbridge/nvidia/mcp55/mcp55_azalia.c
new file mode 100644
index 0000000000..9205808754
--- /dev/null
+++ b/src/southbridge/nvidia/mcp55/mcp55_azalia.c
@@ -0,0 +1,297 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "mcp55.h"
+
+#define HDA_ICII_REG 0x68
+#define   HDA_ICII_BUSY (1 << 0)
+#define   HDA_ICII_VALID  (1 << 1)
+
+static int set_bits(u32 port, u32 mask, u32 val)
+{
+	u32 reg32;
+	int count;
+
+	/* Write (val & mask) to port */
+	val &= mask;
+	reg32 = read32(port);
+	reg32 &= ~mask;
+	reg32 |= val;
+	write32(port, reg32);
+
+	/* Wait for readback of register to
+	 * match what was just written to it
+	 */
+	count = 50;
+	do {
+		/* Wait 1ms based on BKDG wait time */
+		mdelay(1);
+		reg32 = read32(port);
+		reg32 &= mask;
+	} while ((reg32 != val) && --count);
+
+	/* Timeout occured */
+	if (!count)
+		return -1;
+	return 0;
+}
+
+static int codec_detect(u32 base)
+{
+	u32 reg32;
+
+	/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 0) == -1)
+		goto no_codec;
+
+	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 1) == -1)
+		goto no_codec;
+
+	/* Read in Codec location (BAR + 0xe)[2..0]*/
+	reg32 = read32(base + 0xe);
+	reg32 &= 0x0f;
+	if (!reg32)
+		goto no_codec;
+
+	return reg32;
+
+no_codec:
+	/* Codec Not found */
+	/* Put HDA back in reset (BAR + 0x8) [0] */
+	set_bits(base + 0x08, 1, 0);
+	printk(BIOS_DEBUG, "Azalia: No codec!\n");
+	return 0;
+}
+
+u32 * cim_verb_data = NULL;
+u32 cim_verb_data_size = 0;
+
+static u32 find_verb(struct device *dev, u32 viddid, u32 ** verb)
+{
+	int idx=0;
+
+	while (idx < (cim_verb_data_size / sizeof(u32))) {
+		u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
+		if (cim_verb_data[idx] != viddid) {
+			idx += verb_size + 3; // skip verb + header
+			continue;
+		}
+		*verb = &cim_verb_data[idx+3];
+		return verb_size;
+	}
+
+	/* Not all codecs need to load another verb */
+	return 0;
+}
+
+/**
+ *  Wait 50usec for for the codec to indicate it is ready
+ *  no response would imply that the codec is non-operative
+ */
+
+static int wait_for_ready(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+
+	while(timeout--) {
+		u32 reg32 = read32(base +  HDA_ICII_REG);
+		if (!(reg32 & HDA_ICII_BUSY))
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/**
+ *  Wait 50usec for for the codec to indicate that it accepted
+ *  the previous command.  No response would imply that the code
+ *  is non-operative
+ */
+
+static int wait_for_valid(u32 base)
+{
+	u32 reg32;
+
+	/* Send the verb to the codec */
+	reg32 = read32(base + 0x68);
+	reg32 |= (1 << 0) | (1 << 1);
+	write32(base + 0x68, reg32);
+
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+	while(timeout--) {
+		reg32 = read32(base + HDA_ICII_REG);
+		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+			HDA_ICII_VALID)
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+static void codec_init(struct device *dev, u32 base, int addr)
+{
+	u32 reg32;
+	u32 *verb;
+	u32 verb_size;
+	int i;
+
+	printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
+
+	/* 1 */
+	if (wait_for_ready(base) == -1)
+		return;
+
+	reg32 = (addr << 28) | 0x000f0000;
+	write32(base + 0x60, reg32);
+
+	if (wait_for_valid(base) == -1)
+		return;
+
+	reg32 = read32(base + 0x64);
+
+	/* 2 */
+	printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
+	verb_size = find_verb(dev, reg32, &verb);
+
+	if (!verb_size) {
+		printk(BIOS_DEBUG, "Azalia: No verb!\n");
+		return;
+	}
+	printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
+
+	/* 3 */
+	for (i = 0; i < verb_size; i++) {
+		if (wait_for_ready(base) == -1)
+			return;
+
+		write32(base + 0x60, verb[i]);
+
+		if (wait_for_valid(base) == -1)
+			return;
+	}
+	printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
+}
+
+static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+{
+	int i;
+	for (i = 2; i >= 0; i--) {
+		if (codec_mask & (1 << i))
+			codec_init(dev, base, i);
+	}
+}
+
+static void azalia_init(struct device *dev)
+{
+	u32 base;
+	struct resource *res;
+	u32 codec_mask;
+	u8 reg8;
+	u32 reg32;
+
+	/* Set Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+
+	pci_write_config8(dev, 0x3c, 0x0a); // unused?
+
+	reg8 = pci_read_config8(dev, 0x40);
+	reg8 |= (1 << 3); // Clear Clock Detect Bit
+	pci_write_config8(dev, 0x40, reg8);
+	reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
+	pci_write_config8(dev, 0x40, reg8);
+	reg8 |= (1 << 2); // Enable clock detection
+	pci_write_config8(dev, 0x40, reg8);
+	mdelay(1);
+	reg8 = pci_read_config8(dev, 0x40);
+	printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
+
+	//
+	reg8 = pci_read_config8(dev, 0x40); // Audio Control
+	reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
+	pci_write_config8(dev, 0x40, reg8);
+
+	reg8 = pci_read_config8(dev, 0x4d); // Docking Status
+	reg8 &= ~(1 << 7); // Docking not supported
+	pci_write_config8(dev, 0x4d, reg8);
+
+	res = find_resource(dev, 0x10);
+	if (!res)
+		return;
+
+	// NOTE this will break as soon as the Azalia get's a bar above
+	// 4G. Is there anything we can do about it?
+	base = (u32)res->base;
+	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+	codec_mask = codec_detect(base);
+
+	if (codec_mask) {
+		printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
+		codecs_init(dev, base, codec_mask);
+	}
+}
+
+static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations azalia_pci_ops = {
+	.set_subsystem    = azalia_set_subsystem,
+};
+
+static struct device_operations azalia_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= azalia_init,
+	.scan_bus		= 0,
+//	.enable			= mcp55_enable,
+	.ops_pci		= &azalia_pci_ops,
+};
+
+static const struct pci_driver azalia __pci_driver = {
+	.ops	= &azalia_ops,
+	.vendor	= PCI_VENDOR_ID_NVIDIA,
+	.device	= PCI_DEVICE_ID_NVIDIA_MCP55_AZA,
+};
+