diff options
| author | Arne Georg Gleditsch <arne.gleditsch@numascale.com> | 2010-09-09 14:54:07 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-09-09 14:54:07 +0000 |
| commit | d6689ed7813b37c92bbe6058155d67c4757fef26 (patch) | |
| tree | 2067aa432c89740cb808662de827a6d32970d1c3 /src/southbridge/nvidia | |
| parent | e0a000cc12984700c87fea6b153fa4221a125e19 (diff) | |
Please find appended. This patch gets rid of the %gs magic altogether,
fixes a few alignment wrinkles and sets up and registers the MMCONF area
for AMD Fam10h CPUs (where selected by mainboard configuration). It
removes a bit of code that proved troublesome in MMCONF setups from
mcp55_early_setup_car.c, as per earlier discussion.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/nvidia')
| -rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c index fb84f5a36d..e01630dc05 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c @@ -267,8 +267,13 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, - - RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, + /* The following operation hangs when performed via MMCFG: + pci_read_config32(romcc): 00010000:0078: 20040000 + setup_resource_map_x_offset: 10000, 78: 20040000 + pci_write_config32(romcc): 00010000:0078: 19040000 + (hang) + Response missing? */ + /* RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, */ #if MCP55_USE_AZA == 1 RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, |