diff options
| author | Myles Watson <mylesgw@gmail.com> | 2010-03-22 16:33:25 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-03-22 16:33:25 +0000 |
| commit | 08e0fb881093c977488de6e8d701dd69369123ec (patch) | |
| tree | 5a7d8aa8415a0b2143ed6f4d52af87191a33561c /src/southbridge/nvidia | |
| parent | 53b0ea4bf24c0ae51aa9f8447d4ce9d44d46af72 (diff) | |
Fix all the format string warnings.
Some other random warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/nvidia')
| -rw-r--r-- | src/southbridge/nvidia/ck804/ck804_nic.c | 8 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_aza.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/mcp55/mcp55_lpc.c | 4 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/nvidia/ck804/ck804_nic.c b/src/southbridge/nvidia/ck804/ck804_nic.c index cb8015c16b..7678fb50fb 100644 --- a/src/southbridge/nvidia/ck804/ck804_nic.c +++ b/src/southbridge/nvidia/ck804/ck804_nic.c @@ -18,11 +18,11 @@ static void nic_init(struct device *dev) int eeprom_valid = 0; struct southbridge_nvidia_ck804_config *conf; static uint32_t nic_index = 0; - uint8_t *base; + unsigned long base; struct resource *res; res = find_resource(dev, 0x10); - base = (uint8_t*)(unsigned long)res->base; + base = (unsigned long)res->base; #define NvRegPhyInterface 0xC0 #define PHY_RGMII 0x10000000 @@ -76,8 +76,8 @@ static void nic_init(struct device *dev) if (!eeprom_valid) { unsigned long mac_pos; mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ - mac_l = read32((uint8_t*)mac_pos) + nic_index; - mac_h = read32((uint8_t*)mac_pos + 4); + mac_l = read32(mac_pos) + nic_index; + mac_h = read32(mac_pos + 4); } #if 1 /* Set that into NIC MMIO. */ diff --git a/src/southbridge/nvidia/mcp55/mcp55_aza.c b/src/southbridge/nvidia/mcp55/mcp55_aza.c index cea0b49e8c..d4b0e8f2fb 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_aza.c +++ b/src/southbridge/nvidia/mcp55/mcp55_aza.c @@ -230,7 +230,7 @@ static void aza_init(struct device *dev) return; base =(uint8_t *) res->base; - printk(BIOS_DEBUG, "base = %08x\n", base); + printk(BIOS_DEBUG, "base = %p\n", base); codec_mask = codec_detect(base); diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index 869e8392e2..84612890e9 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -80,7 +80,7 @@ static void enable_hpet(struct device *dev) pci_write_config32(dev,0x44, 0xfed00001); hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; - printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address); + printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } static void lpc_init(device_t dev) @@ -224,7 +224,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { case 0x3f8: // COM1 reg |= (1<<0); break; |