Move the v3 resource allocator to v2.

Major changes:
1. Separate resource allocation into:
	A. Read Resources
	B. Avoid fixed resources (constrain limits)
	C. Allocate resources
	D. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources.  All fixed resources will end up outside (above or below) 
the allocated resources.

Domains usually start with base = 0 and limit = 2^address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources.  Some platforms may want to change that, but I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 40 insertions, 28 deletions

diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
index 4faaf08fe9..480394ea09 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c
@@ -248,16 +248,27 @@ static void mcp55_lpc_read_resources(device_t dev)
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
+	/* Get the normal PCI resources of this device. */
+	/* We got one for APIC, or one more for TRAP. */
+	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 /**
@@ -265,7 +276,7 @@ static void mcp55_lpc_read_resources(device_t dev)
  *
  * @param dev the device whos children's resources are to be enabled
  *
- * This function is call by the global enable_resources() indirectly via the
+ * This function is called by the global enable_resources() indirectly via the
  * device_operation::enable_resources() method of devices.
  *
  * Indirect mutual recursion:
@@ -286,7 +297,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev)
 		device_t child;
 		for (child = dev->link[link].children; child; child = child->sibling) {
 			enable_resources(child);
-			if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
+			if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 				for(i=0;i<child->resources;i++) {
 					struct resource *res;
 					unsigned long base, end; // don't need long long
diff --git a/src/southbridge/nvidia/mcp55/mcp55_pci.c b/src/southbridge/nvidia/mcp55/mcp55_pci.c
index 2ae5a49e30..3bc3a1ab18 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_pci.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_pci.c
@@ -23,6 +23,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/resource.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
@@ -33,10 +34,8 @@ static void pci_init(struct device *dev)
 
 	uint32_t dword;
 	uint16_t word;
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	device_t pci_domain_dev;
-	struct resource *mem1, *mem2;
-#endif
+	struct resource *mem, *pref;
 
 	/* System error enable */
 	dword = pci_read_config32(dev, 0x04);
@@ -58,30 +57,32 @@ static void pci_init(struct device *dev)
 	pci_write_config32(dev, 0x4c, dword);
 #endif
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
 	pci_domain_dev = dev->bus->dev;
-	while(pci_domain_dev) {
-		if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break;
+	while (pci_domain_dev) {
+		if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
+			break;
 		pci_domain_dev = pci_domain_dev->bus->dev;
 	}
 
-	if(!pci_domain_dev) return; // impossiable
-	mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit
-	mem2 = find_resource(pci_domain_dev, 2); // mem
-	if(mem1->base > mem2->base) {
-		dword = mem2->base  & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
+	if (!pci_domain_dev)
+		return;		/* Impossible */
+
+	pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
+	mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
+
+	if (!mem)
+		return;		/* Impossible */
+
+	if (!pref || pref->base > mem->base) {
+		dword = mem->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
 	} else {
-		dword = mem1->base  & (0xffff0000UL);
-		printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base);
+		dword = pref->base & (0xffff0000UL);
+		printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
 	}
-#else
-	dword = dev_root.resource[1].base & (0xffff0000UL);
-	printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
-#endif
-	printk_debug("[0x50] <-- 0x%08x\n", dword);
-	pci_write_config32(dev, 0x50, dword); //TOM
 
+	printk_debug("[0x50] <-- 0x%08x\n", dword);
+	pci_write_config32(dev, 0x50, dword);	/* TOM */
 }
 
 static struct pci_operations lops_pci = {