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| author | Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> | 2018-09-02 09:11:28 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-06 10:28:59 +0000 |
| commit | 6f70d51facd3332f2fcc057fe0eed818d4d347c3 (patch) | |
| tree | 3eb2b0c0a91429b255f3799a25a68216d3ef472c /src/southbridge/nvidia/mcp55 | |
| parent | 55597ff2799d0028179f0ce84a5c9cfec4971194 (diff) | |
mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0
DMIC's are now connected to DMIC_CLK0/DMIC_DATA0.
So, enable the pins accordingly.
BUG=b:113744731,b:111106010
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image
Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/28433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/nvidia/mcp55')
0 files changed, 0 insertions, 0 deletions