diff options
| author | Martin Roth <martinroth@google.com> | 2017-06-24 21:30:42 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-13 23:54:56 +0000 |
| commit | 1858d6a90a81aac67cde90190d8a332b2e817c9d (patch) | |
| tree | e9d62ce12354e419a8c055da12d092642fac4d88 /src/southbridge/nvidia/mcp55/early_setup_car.c | |
| parent | 32c27c2f850c64cdbf78acd00f0c2ce4b535af64 (diff) | |
src/southbridge: add IS_ENABLED() around Kconfig symbol references
Change-Id: Ie965cbcf7f7b6f6c9e9a69e2a1ff0ba491246cbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/nvidia/mcp55/early_setup_car.c')
| -rw-r--r-- | src/southbridge/nvidia/mcp55/early_setup_car.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 7f1d03b512..8019a8ef21 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -250,7 +250,7 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, #endif -#if CONFIG_MCP55_USE_AZA +#if IS_ENABLED(CONFIG_MCP55_USE_AZA) RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, #endif @@ -260,7 +260,7 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, MCP55_MB_SETUP #endif -#if CONFIG_MCP55_USE_AZA +#if IS_ENABLED(CONFIG_MCP55_USE_AZA) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3 << 2), (2 << 2), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3 << 2), (2 << 2), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3 << 2), (2 << 2), @@ -284,7 +284,7 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012, -#if CONFIG_MCP55_USE_NIC +#if IS_ENABLED(CONFIG_MCP55_USE_NIC) RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1 << 22) | (1 << 20)), (1 << 22) | (1 << 20), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), |