sb/nvidia/mcp55: Drop support

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.

Change-Id: I7cd33316140f2cdc83949aa5db7e6f1565982543
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36973
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 49 deletions

diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c
deleted file mode 100644
index a3593d3001..0000000000
--- a/src/southbridge/nvidia/mcp55/bootblock.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Tyan Computer
- * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
- * Copyright (C) 2006,2007 AMD
- * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_ops.h>
-#include "mcp55.h"
-
-static void mcp55_enable_rom(void)
-{
-	u8 byte;
-	u16 word;
-	pci_devfn_t addr;
-
-	/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
-
-	addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0);
-
-	/* Set the 15MB enable bits. */
-	byte = pci_read_config8(addr, 0x88);
-	byte |= 0xff; /* 256K */
-	pci_write_config8(addr, 0x88, byte);
-	byte = pci_read_config8(addr, 0x8c);
-	byte |= 0xff; /* 1M */
-	pci_write_config8(addr, 0x8c, byte);
-	word = pci_read_config16(addr, 0x90);
-	word |= 0x7fff; /* 15M */
-	pci_write_config16(addr, 0x90, word);
-}
-
-static void bootblock_southbridge_init(void)
-{
-	mcp55_enable_rom();
-}