diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-05 22:17:30 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-11 23:33:23 +0200 |
| commit | 49a7c37de95531eb2f8037542806ec56240388be (patch) | |
| tree | 10dca0b6e05329afe2e5f2b531087141d27f1fd7 /src/southbridge/nvidia/mcp55/bootblock.c | |
| parent | 571fb1fb4432d7e1e18ef610adbca6971e01573d (diff) | |
southbridge/nvidia: Remove commented code
Change-Id: Ice4a5cae1a289852895012bb55035707b54cefb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16899
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/nvidia/mcp55/bootblock.c')
| -rw-r--r-- | src/southbridge/nvidia/mcp55/bootblock.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index b77463af7a..6d24f568da 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -28,13 +28,8 @@ static void mcp55_enable_rom(void) pci_devfn_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ -#if 0 - /* Default MCP55 LPC single */ - addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0); -#else -// addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0); + addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0); -#endif /* Set the 15MB enable bits. */ byte = pci_read_config8(addr, 0x88); |