diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/southbridge/nvidia/ck804 | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/nvidia/ck804')
| -rw-r--r-- | src/southbridge/nvidia/ck804/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/nvidia/ck804/nic.c | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 105f5cbb61..37baf994bc 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -65,7 +65,7 @@ static void lpc_common_init(device_t dev) /* I/O APIC initialization. */ res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ ASSERT(res != NULL); - setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */ + setup_ioapic(res2mmio(res, 0, 0), 0); /* Don't rename IOAPIC ID. */ #if 1 dword = pci_read_config32(dev, 0xe4); diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c index e285644bec..974ce0d4de 100644 --- a/src/southbridge/nvidia/ck804/nic.c +++ b/src/southbridge/nvidia/ck804/nic.c @@ -33,11 +33,11 @@ static void nic_init(struct device *dev) int eeprom_valid = 0; struct southbridge_nvidia_ck804_config *conf; static u32 nic_index = 0; - unsigned long base; + u8 *base; struct resource *res; res = find_resource(dev, 0x10); - base = (unsigned long)res->base; + base = res2mmio(res, 0, 0); #define NvRegPhyInterface 0xC0 #define PHY_RGMII 0x10000000 @@ -89,10 +89,10 @@ static void nic_init(struct device *dev) /* If that is invalid we will read that from romstrap. */ if (!eeprom_valid) { - unsigned long mac_pos; - mac_pos = 0xffffffd0; /* See romstrap.inc and romstrap.lds. */ + u32 *mac_pos; + mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.lds. */ mac_l = read32(mac_pos) + nic_index; - mac_h = read32(mac_pos + 4); + mac_h = read32(mac_pos + 1); } #if 1 /* Set that into NIC MMIO. */ |