southbridge/nvidia: Remove commented code

Change-Id: Ice4a5cae1a289852895012bb55035707b54cefb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16899
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

5 files changed, 0 insertions, 97 deletions

diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c
index abcb913209..1d4999ccbc 100644
--- a/src/southbridge/nvidia/ck804/early_setup.c
+++ b/src/southbridge/nvidia/ck804/early_setup.c
@@ -300,10 +300,6 @@ static void ck804_early_setup(void)
 	setup_ss_table(CK804B_ANACTRL_IO_BASE + 0xc0, CK804B_ANACTRL_IO_BASE + 0xc4, CK804B_ANACTRL_IO_BASE + 0xc8, cpu_ss_tbl, 64);
 #endif
 
-#if 0
-	dump_io_resources(ANACTRL_IO_BASE);
-	dump_io_resources(SYSCTRL_IO_BASE);
-#endif
 }
 
 static int ck804_early_setup_x(void)
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index d15ef8e178..2b0bdd536b 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -136,12 +136,6 @@ static void lpc_init(device_t dev)
 		printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
 		       (on * 12) + (on >> 1), (on & 1) * 5);
 	}
-#if 0
-	/* Enable Port 92 fast reset (default is enabled). */
-	byte = pci_read_config8(dev, 0xe8);
-	byte |= ~(1 << 3);
-	pci_write_config8(dev, 0xe8, byte);
-#endif
 
 	/* Set up NMI on errors. */
 	byte = inb(0x70);		/* RTC70 */
diff --git a/src/southbridge/nvidia/ck804/pci.c b/src/southbridge/nvidia/ck804/pci.c
index 8ccf80cadf..a9f0f5b225 100644
--- a/src/southbridge/nvidia/ck804/pci.c
+++ b/src/southbridge/nvidia/ck804/pci.c
@@ -33,18 +33,9 @@ static void pci_init(struct device *dev)
 	dword |= (1 << 30);	/* Clear possible errors */
 	pci_write_config32(dev, 0x04, dword);
 
-#if 0
-	word = pci_read_config16(dev, 0x48);
-	word |= (1 << 0);	/* MRL2MRM */
-	word |= (1 << 2);	/* MR2MRM */
-	pci_write_config16(dev, 0x48, word);
-#endif
-
-#if 1
 	dword = pci_read_config32(dev, 0x4c);
 	dword |= 0x00440000;	/* TABORT_SER_ENABLE Park Last Enable. */
 	pci_write_config32(dev, 0x4c, dword);
-#endif
 
 	pci_domain_dev = dev->bus->dev;
 	while (pci_domain_dev) {
diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c
index b67cf28aba..c5dc56e83e 100644
--- a/src/southbridge/nvidia/ck804/sata.c
+++ b/src/southbridge/nvidia/ck804/sata.c
@@ -51,13 +51,6 @@ static void sata_com_reset(struct device *dev, unsigned reset)
 	*(base + 8) = dword;
 	*(base + 0x48) = dword;
 
-#if 0
-	udelay(1000);
-	dword &= ~(0xf);
-	*(base + 8) = dword;
-	*(base + 0x48) = dword;
-#endif
-
 	if (reset)
 		return;
 
@@ -109,17 +102,6 @@ static void sata_init(struct device *dev)
 		dword |= (1 << 1);
 		printk(BIOS_DEBUG, "SATA P\n");
 	}
-#if 0
-	/* Write back */
-	dword |= (1 << 12);
-	dword |= (1 << 14);
-#endif
-
-#if 0
-	/* ADMA */
-	dword |= (1 << 16);
-	dword |= (1 << 17);
-#endif
 
 #if 1
 	/* DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. */
@@ -128,23 +110,6 @@ static void sata_init(struct device *dev)
 #endif
 	pci_write_config32(dev, 0x50, dword);
 
-#if 0
-	/* SLUMBER_DURING_D3 */
-	dword = pci_read_config32(dev, 0x7c);
-	dword &= ~(1 << 4);
-	pci_write_config32(dev, 0x7c, dword);
-
-	dword = pci_read_config32(dev, 0xd0);
-	dword &= ~(0xff << 24);
-	dword |= (0x68 << 24);
-	pci_write_config32(dev, 0xd0, dword);
-
-	dword = pci_read_config32(dev, 0xe0);
-	dword &= ~(0xff << 24);
-	dword |= (0x68 << 24);
-	pci_write_config32(dev, 0xe0, dword);
-#endif
-
 	dword = pci_read_config32(dev, 0xf8);
 	dword |= 2;
 	pci_write_config32(dev, 0xf8, dword);
diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h
index 6d0c510f89..40b8cb7dcd 100644
--- a/src/southbridge/nvidia/ck804/smbus.h
+++ b/src/southbridge/nvidia/ck804/smbus.h
@@ -34,25 +34,6 @@ static inline void smbus_delay(void)
 	outb(0x80, 0x80);
 }
 
-#if 0
-/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
-static int smbus_wait_until_ready(unsigned smbus_io_base)
-{
-	unsigned long loops;
-	loops = SMBUS_TIMEOUT;
-	do {
-		unsigned char val;
-		smbus_delay();
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;
-		if (val == 0)
-			return 0;
-		outb(val, smbus_io_base + SMBHSTSTAT);
-	} while (--loops);
-	return -2;
-}
-#endif
-
 static int smbus_wait_until_done(unsigned smbus_io_base)
 {
 	unsigned long loops;
@@ -72,12 +53,6 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
 {
 	unsigned char global_status_register, byte;
 
-#if 0
-	/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
-	if (smbus_wait_until_ready(smbus_io_base) < 0)
-		return -2;
-#endif
-
 	/* Set the device I'm talking to. */
 	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
 	smbus_delay();
@@ -112,12 +87,6 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device,
 {
 	unsigned global_status_register;
 
-#if 0
-	/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
-	if (smbus_wait_until_ready(smbus_io_base) < 0)
-		return -2;
-#endif
-
 	outb(val, smbus_io_base + SMBHSTDAT0);
 	smbus_delay();
 
@@ -151,12 +120,6 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
 {
 	unsigned char global_status_register, byte;
 
-#if 0
-	/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
-	if (smbus_wait_until_ready(smbus_io_base) < 0)
-		return -2;
-#endif
-
 	/* Set the device I'm talking to. */
 	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
 	smbus_delay();
@@ -191,12 +154,6 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device,
 {
 	unsigned global_status_register;
 
-#if 0
-	/* Not needed, upon write to PRTCL, the status will be auto-cleared. */
-	if (smbus_wait_until_ready(smbus_io_base) < 0)
-		return -2;
-#endif
-
 	outb(val, smbus_io_base + SMBHSTDAT0);
 	smbus_delay();