diff options
| author | Nico Huber <nico.h@gmx.de> | 2018-01-14 12:34:43 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-23 05:25:41 +0000 |
| commit | ff4025c5f789b80e6552dd887c34c34642a98c64 (patch) | |
| tree | 852784fb6548c414d41dbdc93f4de6b5b191f9a6 /src/southbridge/intel | |
| parent | 101485c73dbb7eb8d89fbfda1c1bf9a5e495b536 (diff) | |
sb/intel/bd82x6x: Reduce function-disable mess
Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.
To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.
Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_rcba.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 2 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index eeecb5fdbe..9bd3a26e22 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -63,3 +63,9 @@ southbridge_configure_default_intmap(void) /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); } + +void +southbridge_rcba_config(void) +{ + RCBA32(FD) = PCH_DISABLE_ALWAYS; +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 83d9d8d1dd..b094826336 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -85,6 +85,8 @@ int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); void early_thermal_init(void); void southbridge_configure_default_intmap(void); +void southbridge_rcba_config(void); +void mainboard_rcba_config(void); void early_pch_init_native(void); int southbridge_detect_s3_resume(void); |