diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-09-08 13:30:17 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-04-14 20:54:16 +0000 |
| commit | f58e53601669133b1f23eb2a580171075054418f (patch) | |
| tree | b54c13b170bc73bfc99dbd46724254bbe00c1de8 /src/southbridge/intel | |
| parent | 9cd1bf2c17932e5985c5156dfa5fea76c25da725 (diff) | |
lynxpoint/broadwell: Correct PCH-LP PCIe ASPM check
Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM
on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also
uses bit 29 for root port #6. Correct the bit used in the check, as well
as the surrounding comments.
Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 7f5e1face6..0c17c9c22e 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -518,17 +518,17 @@ static void pch_pcie_early(struct device *dev) break; case 5: /* - * Bit 28 of b0d28f4 0x32c register correspond to - * Root Ports 4:1. + * Bit 28 of b0d28f4 0x32c register corresponds to + * Root Port 5. */ do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); break; case 6: /* - * Bit 28 of b0d28f5 0x32c register correspond to - * Root Ports 4:1. + * Bit 29 of b0d28f5 0x32c register corresponds to + * Root Port 6. */ - do_aspm = !!(rpc.b0d28f5_32c & (1 << 28)); + do_aspm = !!(rpc.b0d28f5_32c & (1 << 29)); break; } } else { |