diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/southbridge/intel | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel')
67 files changed, 598 insertions, 546 deletions
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index bef88abea4..32223c2c34 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -35,7 +35,7 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static int set_bits(u32 port, u32 mask, u32 val) +static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -64,7 +64,7 @@ static int set_bits(u32 port, u32 mask, u32 val) return 0; } -static int codec_detect(u32 base) +static int codec_detect(u8 *base) { u8 reg8; @@ -73,7 +73,8 @@ static int codec_detect(u32 base) goto no_codec; /* Write back the value once reset bit is set. */ - write16(base + 0x0, read16(base + 0x0)); + write16(base + 0x0, + read16(base + 0x0)); /* Read in Codec location (BAR + 0xe)[2..0]*/ reg8 = read8(base + 0xe); @@ -114,14 +115,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) * no response would imply that the codec is non-operative */ -static int wait_for_ready(u32 base) +static int wait_for_ready(u8 *base) { /* Use a 1msec timeout */ int timeout = 1000; while(timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -136,7 +137,7 @@ static int wait_for_ready(u32 base) * is non-operative */ -static int wait_for_valid(u32 base) +static int wait_for_valid(u8 *base) { u32 reg32; @@ -159,7 +160,7 @@ static int wait_for_valid(u32 base) return -1; } -static void codec_init(struct device *dev, u32 base, int addr) +static void codec_init(struct device *dev, u8 *base, int addr) { u32 reg32; const u32 *verb; @@ -207,7 +208,7 @@ static void codec_init(struct device *dev, u32 base, int addr) printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } -static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; for (i = 3; i >= 0; i--) { @@ -228,7 +229,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void azalia_init(struct device *dev) { - u32 base; + u8 *base; struct resource *res; u32 codec_mask; u8 reg8; @@ -242,7 +243,7 @@ static void azalia_init(struct device *dev) // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? - base = (u32)res->base; + base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); if (RCBA32(0x2030) & (1 << 31)) { diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index b1b53af3ad..52c21728e6 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -53,7 +53,7 @@ static void enable_port80_on_lpc(void) pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); /* Enable port 80 POST on LPC */ - pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); + pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); #if 0 RCBA32(GCS) &= (~0x04); #else diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c index 0863f3462c..5f4272890a 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_native.c +++ b/src/southbridge/intel/bd82x6x/early_pch_native.c @@ -37,7 +37,7 @@ static void wait_2338 (void) { - while (read8 (DEFAULT_RCBA | 0x2338) & 1); + while (read8 (DEFAULT_RCBA + 0x2338) & 1); } static u32 @@ -45,13 +45,13 @@ read_2338 (u32 edx) { u32 ret; - write32 (DEFAULT_RCBA | 0x2330, edx); - write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338) + write32 (DEFAULT_RCBA + 0x2330, edx); + write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338) & 0x1ff) | 0x600); wait_2338 (); - ret = read32 (DEFAULT_RCBA | 0x2334); + ret = read32 (DEFAULT_RCBA + 0x2334); wait_2338 (); - read8 (DEFAULT_RCBA | 0x2338); + read8 (DEFAULT_RCBA + 0x2338); return ret; } @@ -59,15 +59,15 @@ static void write_2338 (u32 edx, u32 val) { read_2338 (edx); - write16 (DEFAULT_RCBA | 0x2338, (read16 (DEFAULT_RCBA | 0x2338) + write16 (DEFAULT_RCBA + 0x2338, (read16 (DEFAULT_RCBA + 0x2338) & 0x1ff) | 0x600); wait_2338 (); - write32 (DEFAULT_RCBA | 0x2334, val); + write32 (DEFAULT_RCBA + 0x2334, val); wait_2338 (); - write16 (DEFAULT_RCBA | 0x2338, - (read16 (DEFAULT_RCBA | 0x2338) & 0x1ff) | 0x600); - read8 (DEFAULT_RCBA | 0x2338); + write16 (DEFAULT_RCBA + 0x2338, + (read16 (DEFAULT_RCBA + 0x2338) & 0x1ff) | 0x600); + read8 (DEFAULT_RCBA + 0x2338); } @@ -76,214 +76,214 @@ init_dmi (void) { int i; - write32 (DEFAULT_DMIBAR | 0x0914, - read32 (DEFAULT_DMIBAR | 0x0914) | 0x80000000); - write32 (DEFAULT_DMIBAR | 0x0934, - read32 (DEFAULT_DMIBAR | 0x0934) | 0x80000000); + write32 (DEFAULT_DMIBAR + 0x0914, + read32 (DEFAULT_DMIBAR + 0x0914) | 0x80000000); + write32 (DEFAULT_DMIBAR + 0x0934, + read32 (DEFAULT_DMIBAR + 0x0934) | 0x80000000); for (i = 0; i < 4; i++) { - write32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4), - read32 (DEFAULT_DMIBAR | 0x0a00 | (i << 4)) & 0xf3ffffff); - write32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4), - read32 (DEFAULT_DMIBAR | 0x0a04 | (i << 4)) | 0x800); + write32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4), + read32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4)) & 0xf3ffffff); + write32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4), + read32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4)) | 0x800); } - write32 (DEFAULT_DMIBAR | 0x0c30, (read32 (DEFAULT_DMIBAR | 0x0c30) + write32 (DEFAULT_DMIBAR + 0x0c30, (read32 (DEFAULT_DMIBAR + 0x0c30) & 0xfffffff) | 0x40000000); for (i = 0; i < 2; i++) { - write32 (DEFAULT_DMIBAR | 0x0904 | (i << 5), - read32 (DEFAULT_DMIBAR | 0x0904 | (i << 5)) & 0xfe3fffff); - write32 (DEFAULT_DMIBAR | 0x090c | (i << 5), - read32 (DEFAULT_DMIBAR | 0x090c | (i << 5)) & 0xfff1ffff); + write32 (DEFAULT_DMIBAR + 0x0904 + (i << 5), + read32 (DEFAULT_DMIBAR + 0x0904 + (i << 5)) & 0xfe3fffff); + write32 (DEFAULT_DMIBAR + 0x090c + (i << 5), + read32 (DEFAULT_DMIBAR + 0x090c + (i << 5)) & 0xfff1ffff); } - write32 (DEFAULT_DMIBAR | 0x090c, - read32 (DEFAULT_DMIBAR | 0x090c) & 0xfe1fffff); - write32 (DEFAULT_DMIBAR | 0x092c, - read32 (DEFAULT_DMIBAR | 0x092c) & 0xfe1fffff); - read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR | 0x0904, 0x7a1842ec); - read32 (DEFAULT_DMIBAR | 0x090c); // !!! = 0x00000208 - write32 (DEFAULT_DMIBAR | 0x090c, 0x00000128); - read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR | 0x0924, 0x7a1842ec); - read32 (DEFAULT_DMIBAR | 0x092c); // !!! = 0x00000208 - write32 (DEFAULT_DMIBAR | 0x092c, 0x00000128); - read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008); - read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008); - read32 (DEFAULT_DMIBAR | 0x0c04); // !!! = 0x2e680008 - write32 (DEFAULT_DMIBAR | 0x0c04, 0x2e680008); - read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1842ec); - read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1842ec); - read32 (DEFAULT_DMIBAR | 0x0910); // !!! = 0x00006300 - write32 (DEFAULT_DMIBAR | 0x0910, 0x00004300); - read32 (DEFAULT_DMIBAR | 0x0930); // !!! = 0x00006300 - write32 (DEFAULT_DMIBAR | 0x0930, 0x00004300); - read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08 - write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08); - read32 (DEFAULT_DMIBAR | 0x0a04); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR | 0x0a04, 0x0c0718f0); - read32 (DEFAULT_DMIBAR | 0x0a14); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR | 0x0a14, 0x0c0718f0); - read32 (DEFAULT_DMIBAR | 0x0a24); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR | 0x0a24, 0x0c0718f0); - read32 (DEFAULT_DMIBAR | 0x0a34); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR | 0x0a34, 0x0c0718f0); - read32 (DEFAULT_DMIBAR | 0x0900); // !!! = 0x50000000 - write32 (DEFAULT_DMIBAR | 0x0900, 0x50000000); - read32 (DEFAULT_DMIBAR | 0x0920); // !!! = 0x50000000 - write32 (DEFAULT_DMIBAR | 0x0920, 0x50000000); - read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff); - read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff); - read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR | 0x0700, 0x46139008); - read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR | 0x0720, 0x46139008); - read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1842ec - write32 (DEFAULT_DMIBAR | 0x0904, 0x3a1846ec); - read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1842ec - write32 (DEFAULT_DMIBAR | 0x0924, 0x3a1846ec); - read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR | 0x0908); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR | 0x0908, 0x51ffffff); - read32 (DEFAULT_DMIBAR | 0x0928); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR | 0x0928, 0x51ffffff); - read32 (DEFAULT_DMIBAR | 0x0c00); // !!! = 0x29700c08 - write32 (DEFAULT_DMIBAR | 0x0c00, 0x29700c08); - read32 (DEFAULT_DMIBAR | 0x0c0c); // !!! = 0x16063400 - write32 (DEFAULT_DMIBAR | 0x0c0c, 0x00063400); - read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR | 0x0700, 0x46339008); - read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR | 0x0720, 0x46339008); - read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x46339008 - write32 (DEFAULT_DMIBAR | 0x0700, 0x45339008); - read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x46339008 - write32 (DEFAULT_DMIBAR | 0x0720, 0x45339008); - read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45339008 - write32 (DEFAULT_DMIBAR | 0x0700, 0x453b9008); - read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45339008 - write32 (DEFAULT_DMIBAR | 0x0720, 0x453b9008); - read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x453b9008 - write32 (DEFAULT_DMIBAR | 0x0700, 0x45bb9008); - read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x453b9008 - write32 (DEFAULT_DMIBAR | 0x0720, 0x45bb9008); - read32 (DEFAULT_DMIBAR | 0x0700); // !!! = 0x45bb9008 - write32 (DEFAULT_DMIBAR | 0x0700, 0x45fb9008); - read32 (DEFAULT_DMIBAR | 0x0720); // !!! = 0x45bb9008 - write32 (DEFAULT_DMIBAR | 0x0720, 0x45fb9008); - read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a080 - write32 (DEFAULT_DMIBAR | 0x0914, 0x9021a280); - read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a080 - write32 (DEFAULT_DMIBAR | 0x0934, 0x9021a280); - read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9021a280 - write32 (DEFAULT_DMIBAR | 0x0914, 0x9821a280); - read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9021a280 - write32 (DEFAULT_DMIBAR | 0x0934, 0x9821a280); - read32 (DEFAULT_DMIBAR | 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a00, 0x03242018); - read32 (DEFAULT_DMIBAR | 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a10, 0x03242018); - read32 (DEFAULT_DMIBAR | 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a20, 0x03242018); - read32 (DEFAULT_DMIBAR | 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR | 0x0a30, 0x03242018); - read32 (DEFAULT_DMIBAR | 0x0258); // !!! = 0x40000600 - write32 (DEFAULT_DMIBAR | 0x0258, 0x60000600); - read32 (DEFAULT_DMIBAR | 0x0904); // !!! = 0x3a1846ec - write32 (DEFAULT_DMIBAR | 0x0904, 0x2a1846ec); - read32 (DEFAULT_DMIBAR | 0x0914); // !!! = 0x9821a280 - write32 (DEFAULT_DMIBAR | 0x0914, 0x98200280); - read32 (DEFAULT_DMIBAR | 0x0924); // !!! = 0x3a1846ec - write32 (DEFAULT_DMIBAR | 0x0924, 0x2a1846ec); - read32 (DEFAULT_DMIBAR | 0x0934); // !!! = 0x9821a280 - write32 (DEFAULT_DMIBAR | 0x0934, 0x98200280); - read32 (DEFAULT_DMIBAR | 0x022c); // !!! = 0x00c26460 - write32 (DEFAULT_DMIBAR | 0x022c, 0x00c2403c); - read8 (DEFAULT_RCBA | 0x21a4); // !!! = 0x42 + write32 (DEFAULT_DMIBAR + 0x090c, + read32 (DEFAULT_DMIBAR + 0x090c) & 0xfe1fffff); + write32 (DEFAULT_DMIBAR + 0x092c, + read32 (DEFAULT_DMIBAR + 0x092c) & 0xfe1fffff); + read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec + write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec); + read32 (DEFAULT_DMIBAR + 0x090c); // !!! = 0x00000208 + write32 (DEFAULT_DMIBAR + 0x090c, 0x00000128); + read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec + write32 (DEFAULT_DMIBAR + 0x0924, 0x7a1842ec); + read32 (DEFAULT_DMIBAR + 0x092c); // !!! = 0x00000208 + write32 (DEFAULT_DMIBAR + 0x092c, 0x00000128); + read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 + write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008); + read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 + write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008); + read32 (DEFAULT_DMIBAR + 0x0c04); // !!! = 0x2e680008 + write32 (DEFAULT_DMIBAR + 0x0c04, 0x2e680008); + read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec + write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1842ec); + read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec + write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1842ec); + read32 (DEFAULT_DMIBAR + 0x0910); // !!! = 0x00006300 + write32 (DEFAULT_DMIBAR + 0x0910, 0x00004300); + read32 (DEFAULT_DMIBAR + 0x0930); // !!! = 0x00006300 + write32 (DEFAULT_DMIBAR + 0x0930, 0x00004300); + read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042010 + write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042010 + write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042010 + write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042010 + write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08 + write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08); + read32 (DEFAULT_DMIBAR + 0x0a04); // !!! = 0x0c0708f0 + write32 (DEFAULT_DMIBAR + 0x0a04, 0x0c0718f0); + read32 (DEFAULT_DMIBAR + 0x0a14); // !!! = 0x0c0708f0 + write32 (DEFAULT_DMIBAR + 0x0a14, 0x0c0718f0); + read32 (DEFAULT_DMIBAR + 0x0a24); // !!! = 0x0c0708f0 + write32 (DEFAULT_DMIBAR + 0x0a24, 0x0c0718f0); + read32 (DEFAULT_DMIBAR + 0x0a34); // !!! = 0x0c0708f0 + write32 (DEFAULT_DMIBAR + 0x0a34, 0x0c0718f0); + read32 (DEFAULT_DMIBAR + 0x0900); // !!! = 0x50000000 + write32 (DEFAULT_DMIBAR + 0x0900, 0x50000000); + read32 (DEFAULT_DMIBAR + 0x0920); // !!! = 0x50000000 + write32 (DEFAULT_DMIBAR + 0x0920, 0x50000000); + read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff + write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff); + read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff + write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff); + read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 + write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008); + read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 + write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008); + read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1842ec + write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1846ec); + read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1842ec + write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1846ec); + read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); + read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff + write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff); + read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff + write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff); + read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08 + write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08); + read32 (DEFAULT_DMIBAR + 0x0c0c); // !!! = 0x16063400 + write32 (DEFAULT_DMIBAR + 0x0c0c, 0x00063400); + read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 + write32 (DEFAULT_DMIBAR + 0x0700, 0x46339008); + read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 + write32 (DEFAULT_DMIBAR + 0x0720, 0x46339008); + read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46339008 + write32 (DEFAULT_DMIBAR + 0x0700, 0x45339008); + read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46339008 + write32 (DEFAULT_DMIBAR + 0x0720, 0x45339008); + read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45339008 + write32 (DEFAULT_DMIBAR + 0x0700, 0x453b9008); + read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45339008 + write32 (DEFAULT_DMIBAR + 0x0720, 0x453b9008); + read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x453b9008 + write32 (DEFAULT_DMIBAR + 0x0700, 0x45bb9008); + read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x453b9008 + write32 (DEFAULT_DMIBAR + 0x0720, 0x45bb9008); + read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45bb9008 + write32 (DEFAULT_DMIBAR + 0x0700, 0x45fb9008); + read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45bb9008 + write32 (DEFAULT_DMIBAR + 0x0720, 0x45fb9008); + read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a080 + write32 (DEFAULT_DMIBAR + 0x0914, 0x9021a280); + read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a080 + write32 (DEFAULT_DMIBAR + 0x0934, 0x9021a280); + read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a280 + write32 (DEFAULT_DMIBAR + 0x0914, 0x9821a280); + read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a280 + write32 (DEFAULT_DMIBAR + 0x0934, 0x9821a280); + read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a00, 0x03242018); + read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a10, 0x03242018); + read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a20, 0x03242018); + read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 + write32 (DEFAULT_DMIBAR + 0x0a30, 0x03242018); + read32 (DEFAULT_DMIBAR + 0x0258); // !!! = 0x40000600 + write32 (DEFAULT_DMIBAR + 0x0258, 0x60000600); + read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1846ec + write32 (DEFAULT_DMIBAR + 0x0904, 0x2a1846ec); + read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9821a280 + write32 (DEFAULT_DMIBAR + 0x0914, 0x98200280); + read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1846ec + write32 (DEFAULT_DMIBAR + 0x0924, 0x2a1846ec); + read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9821a280 + write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280); + read32 (DEFAULT_DMIBAR + 0x022c); // !!! = 0x00c26460 + write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c); + read8 (DEFAULT_RCBA + 0x21a4); // !!! = 0x42 - read32 (DEFAULT_RCBA | 0x21a4); // !!! = 0x00012c42 - read32 (DEFAULT_RCBA | 0x2340); // !!! = 0x0013001b - write32 (DEFAULT_RCBA | 0x2340, 0x003a001b); - read8 (DEFAULT_RCBA | 0x21b0); // !!! = 0x01 - write8 (DEFAULT_RCBA | 0x21b0, 0x02); - read32 (DEFAULT_DMIBAR | 0x0084); // !!! = 0x0041ac41 - write32 (DEFAULT_DMIBAR | 0x0084, 0x0041ac42); - read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00 - write8 (DEFAULT_DMIBAR | 0x0088, 0x20); - read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0041 - read8 (DEFAULT_DMIBAR | 0x0088); // !!! = 0x00 - write8 (DEFAULT_DMIBAR | 0x0088, 0x20); - read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042 - read16 (DEFAULT_DMIBAR | 0x008a); // !!! = 0x0042 + read32 (DEFAULT_RCBA + 0x21a4); // !!! = 0x00012c42 + read32 (DEFAULT_RCBA + 0x2340); // !!! = 0x0013001b + write32 (DEFAULT_RCBA + 0x2340, 0x003a001b); + read8 (DEFAULT_RCBA + 0x21b0); // !!! = 0x01 + write8 (DEFAULT_RCBA + 0x21b0, 0x02); + read32 (DEFAULT_DMIBAR + 0x0084); // !!! = 0x0041ac41 + write32 (DEFAULT_DMIBAR + 0x0084, 0x0041ac42); + read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00 + write8 (DEFAULT_DMIBAR + 0x0088, 0x20); + read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0041 + read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00 + write8 (DEFAULT_DMIBAR + 0x0088, 0x20); + read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042 + read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042 - read32 (DEFAULT_DMIBAR | 0x0014); // !!! = 0x8000007f - write32 (DEFAULT_DMIBAR | 0x0014, 0x80000019); - read32 (DEFAULT_DMIBAR | 0x0020); // !!! = 0x01000000 - write32 (DEFAULT_DMIBAR | 0x0020, 0x81000022); - read32 (DEFAULT_DMIBAR | 0x002c); // !!! = 0x02000000 - write32 (DEFAULT_DMIBAR | 0x002c, 0x82000044); - read32 (DEFAULT_DMIBAR | 0x0038); // !!! = 0x07000080 - write32 (DEFAULT_DMIBAR | 0x0038, 0x87000080); - read8 (DEFAULT_DMIBAR | 0x0004); // !!! = 0x00 - write8 (DEFAULT_DMIBAR | 0x0004, 0x01); + read32 (DEFAULT_DMIBAR + 0x0014); // !!! = 0x8000007f + write32 (DEFAULT_DMIBAR + 0x0014, 0x80000019); + read32 (DEFAULT_DMIBAR + 0x0020); // !!! = 0x01000000 + write32 (DEFAULT_DMIBAR + 0x0020, 0x81000022); + read32 (DEFAULT_DMIBAR + 0x002c); // !!! = 0x02000000 + write32 (DEFAULT_DMIBAR + 0x002c, 0x82000044); + read32 (DEFAULT_DMIBAR + 0x0038); // !!! = 0x07000080 + write32 (DEFAULT_DMIBAR + 0x0038, 0x87000080); + read8 (DEFAULT_DMIBAR + 0x0004); // !!! = 0x00 + write8 (DEFAULT_DMIBAR + 0x0004, 0x01); - read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x01200654 - write32 (DEFAULT_RCBA | 0x0050, 0x01200654); - read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x01200654 - write32 (DEFAULT_RCBA | 0x0050, 0x012a0654); - read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x012a0654 - read8 (DEFAULT_RCBA | 0x1114); // !!! = 0x00 - write8 (DEFAULT_RCBA | 0x1114, 0x05); - read32 (DEFAULT_RCBA | 0x2014); // !!! = 0x80000011 - write32 (DEFAULT_RCBA | 0x2014, 0x80000019); - read32 (DEFAULT_RCBA | 0x2020); // !!! = 0x00000000 - write32 (DEFAULT_RCBA | 0x2020, 0x81000022); - read32 (DEFAULT_RCBA | 0x2020); // !!! = 0x81000022 - read32 (DEFAULT_RCBA | 0x2030); // !!! = 0x00000000 - write32 (DEFAULT_RCBA | 0x2030, 0x82000044); - read32 (DEFAULT_RCBA | 0x2030); // !!! = 0x82000044 - read32 (DEFAULT_RCBA | 0x2040); // !!! = 0x00000000 - write32 (DEFAULT_RCBA | 0x2040, 0x87000080); - read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x012a0654 - write32 (DEFAULT_RCBA | 0x0050, 0x812a0654); - read32 (DEFAULT_RCBA | 0x0050); // !!! = 0x812a0654 - read16 (DEFAULT_RCBA | 0x201a); // !!! = 0x0000 - read16 (DEFAULT_RCBA | 0x2026); // !!! = 0x0000 - read16 (DEFAULT_RCBA | 0x2036); // !!! = 0x0000 - read16 (DEFAULT_RCBA | 0x2046); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR | 0x001a); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR | 0x0026); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR | 0x0032); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR | 0x003e); // !!! = 0x0000 + read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654 + write32 (DEFAULT_RCBA + 0x0050, 0x01200654); + read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654 + write32 (DEFAULT_RCBA + 0x0050, 0x012a0654); + read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654 + read8 (DEFAULT_RCBA + 0x1114); // !!! = 0x00 + write8 (DEFAULT_RCBA + 0x1114, 0x05); + read32 (DEFAULT_RCBA + 0x2014); // !!! = 0x80000011 + write32 (DEFAULT_RCBA + 0x2014, 0x80000019); + read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x00000000 + write32 (DEFAULT_RCBA + 0x2020, 0x81000022); + read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x81000022 + read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x00000000 + write32 (DEFAULT_RCBA + 0x2030, 0x82000044); + read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x82000044 + read32 (DEFAULT_RCBA + 0x2040); // !!! = 0x00000000 + write32 (DEFAULT_RCBA + 0x2040, 0x87000080); + read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654 + write32 (DEFAULT_RCBA + 0x0050, 0x812a0654); + read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x812a0654 + read16 (DEFAULT_RCBA + 0x201a); // !!! = 0x0000 + read16 (DEFAULT_RCBA + 0x2026); // !!! = 0x0000 + read16 (DEFAULT_RCBA + 0x2036); // !!! = 0x0000 + read16 (DEFAULT_RCBA + 0x2046); // !!! = 0x0000 + read16 (DEFAULT_DMIBAR + 0x001a); // !!! = 0x0000 + read16 (DEFAULT_DMIBAR + 0x0026); // !!! = 0x0000 + read16 (DEFAULT_DMIBAR + 0x0032); // !!! = 0x0000 + read16 (DEFAULT_DMIBAR + 0x003e); // !!! = 0x0000 } void @@ -292,21 +292,21 @@ early_pch_init_native (void) pcie_write_config8 (SOUTHBRIDGE, 0xa6, pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2); - write32 (DEFAULT_RCBA | 0x2088, 0x00109000); - read32 (DEFAULT_RCBA | 0x20ac); // !!! = 0x00000000 - write32 (DEFAULT_RCBA | 0x20ac, 0x40000000); - write32 (DEFAULT_RCBA | 0x100c, 0x01110000); - write8 (DEFAULT_RCBA | 0x2340, 0x1b); - read32 (DEFAULT_RCBA | 0x2314); // !!! = 0x0a080000 - write32 (DEFAULT_RCBA | 0x2314, 0x0a280000); - read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xc809605b - write32 (DEFAULT_RCBA | 0x2310, 0xa809605b); - write32 (DEFAULT_RCBA | 0x2324, 0x00854c74); - read8 (DEFAULT_RCBA | 0x0400); // !!! = 0x00 - read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xa809605b - write32 (DEFAULT_RCBA | 0x2310, 0xa809605b); - read32 (DEFAULT_RCBA | 0x2310); // !!! = 0xa809605b - write32 (DEFAULT_RCBA | 0x2310, 0xa809605b); + write32 (DEFAULT_RCBA + 0x2088, 0x00109000); + read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000 + write32 (DEFAULT_RCBA + 0x20ac, 0x40000000); + write32 (DEFAULT_RCBA + 0x100c, 0x01110000); + write8 (DEFAULT_RCBA + 0x2340, 0x1b); + read32 (DEFAULT_RCBA + 0x2314); // !!! = 0x0a080000 + write32 (DEFAULT_RCBA + 0x2314, 0x0a280000); + read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xc809605b + write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); + write32 (DEFAULT_RCBA + 0x2324, 0x00854c74); + read8 (DEFAULT_RCBA + 0x0400); // !!! = 0x00 + read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b + write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); + read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b + write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); write_2338 (0xea007f62, 0x00590133); write_2338 (0xec007f62, 0x00590133); diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 02ec9a7436..f2d04dd8a8 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -23,6 +23,21 @@ #include "cpu/intel/model_206ax/model_206ax.h" #include <cpu/x86/msr.h> +static void write8p(uintptr_t addr, uint32_t val) +{ + write8((u8 *)addr, val); +} + +static void write16p(uintptr_t addr, uint32_t val) +{ + write16((u16 *)addr, val); +} + +static uint16_t read16p (uintptr_t addr) +{ + return read16((u16 *)addr); +} + /* Early thermal init, must be done prior to giving ME its memory which is done at the end of raminit. */ void early_thermal_init(void) @@ -41,30 +56,30 @@ void early_thermal_init(void) pci_read_config32(dev, 0x40) | 5); - write16 (0x40000004, 0x3a2b); - write8 (0x4000000c, 0xff); - write8 (0x4000000d, 0x00); - write8 (0x4000000e, 0x40); - write8 (0x40000082, 0x00); - write8 (0x40000001, 0xba); + write16p (0x40000004, 0x3a2b); + write8p (0x4000000c, 0xff); + write8p (0x4000000d, 0x00); + write8p (0x4000000e, 0x40); + write8p (0x40000082, 0x00); + write8p (0x40000001, 0xba); /* Perform init. */ /* Configure TJmax. */ msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6); + write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); /* Northbridge temperature slope and offset. */ - write16(0x40000016, 0x808c); + write16p(0x40000016, 0x808c); - write16 (0x40000014, 0xde87); + write16p (0x40000014, 0xde87); /* Enable thermal data reporting, processor, PCH and northbridge. */ - write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0); + write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); /* Disable temporary BAR. */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); pci_write_config32(dev, 0x40, 0); - write32 (DEFAULT_RCBA | 0x38b0, - (read32 (DEFAULT_RCBA | 0x38b0) & 0xffff8003) | 0x403c); + write32 (DEFAULT_RCBA + 0x38b0, + (read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); } diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c index b8247c6025..b267f95eb7 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_native.c +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -43,32 +43,32 @@ early_usb_init (const struct southbridge_usb_port *portmap) /* Unlock registers. */ outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); for (i = 0; i < 14; i++) - write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), + write32 (DEFAULT_RCBABASE + (0x3500 + 4 * i), currents[portmap[i].current]); for (i = 0; i < 10; i++) - write32 (DEFAULT_RCBABASE | (0x3538 + 4 * i), 0); + write32 (DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); for (i = 0; i < 8; i++) - write32 (DEFAULT_RCBABASE | (0x3560 + 4 * i), rcba_dump[i]); + write32 (DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); for (i = 0; i < 8; i++) - write32 (DEFAULT_RCBABASE | (0x3580 + 4 * i), 0); + write32 (DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); reg32 = 0; for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); - write32 (DEFAULT_RCBABASE | USBPDO, reg32); + write32 (DEFAULT_RCBABASE + USBPDO, reg32); reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); - write32 (DEFAULT_RCBABASE | USBOCM1, reg32); + write32 (DEFAULT_RCBABASE + USBOCM1, reg32); reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); - write32 (DEFAULT_RCBABASE | USBOCM2, reg32); + write32 (DEFAULT_RCBABASE + USBOCM2, reg32); for (i = 0; i < 22; i++) - write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0); + write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 11b765adc6..c323f738fc 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -59,17 +59,17 @@ static void pch_enable_ioapic(struct device *dev) /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(IO_APIC_ADDR, 0x02); + set_ioapic_id(VIO_APIC_VADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read(IO_APIC_ADDR, 0x01); - io_apic_write(IO_APIC_ADDR, 0x01, reg32); + reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x01, reg32); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 901e71dd5e..df188308cf 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -64,7 +64,7 @@ static const char *me_bios_path_values[] = { #endif /* MMIO base address for MEI interface */ -static u32 mei_base_address; +static u32 *mei_base_address; #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) static inline void mei_read_dword_ptr(void *ptr, int offset) { - u32 dword = read32(mei_base_address + offset); + u32 dword = read32(mei_base_address + (offset/sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } @@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); + write32(mei_base_address + (offset/sizeof(u32)), dword); mei_dump(ptr, dword, offset, "WRITE"); } @@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr) static inline void write_cb(u32 dword) { - write32(mei_base_address + MEI_H_CB_WW, dword); + write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { - u32 dword = read32(mei_base_address + MEI_ME_CB_RW); + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); return dword; } @@ -501,11 +501,11 @@ static void intel_me7_finalize_smm(void) struct me_hfs hfs; u32 reg32; - mei_base_address = - pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + mei_base_address = (u32 *) + (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == 0xfffffff0) + if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ @@ -627,7 +627,7 @@ static int intel_mei_setup(device_t dev) printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; } - mei_base_address = res->base; + mei_base_address = (u32*)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index e25b3b8c4f..3fa326962a 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -66,7 +66,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data); #endif /* MMIO base address for MEI interface */ -static u32 mei_base_address; +static u32 *mei_base_address; #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -108,7 +108,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) static inline void mei_read_dword_ptr(void *ptr, int offset) { - u32 dword = read32(mei_base_address + offset); + u32 dword = read32(mei_base_address + (offset/sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } @@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); + write32(mei_base_address + (offset/sizeof(u32)), dword); mei_dump(ptr, dword, offset, "WRITE"); } @@ -147,13 +147,13 @@ static inline void read_me_csr(struct mei_csr *csr) static inline void write_cb(u32 dword) { - write32(mei_base_address + MEI_H_CB_WW, dword); + write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { - u32 dword = read32(mei_base_address + MEI_ME_CB_RW); + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); return dword; } @@ -495,11 +495,11 @@ void intel_me8_finalize_smm(void) struct me_hfs hfs; u32 reg32; - mei_base_address = - pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + mei_base_address = (void *) + (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == 0xfffffff0) + if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ @@ -614,7 +614,7 @@ static int intel_mei_setup(device_t dev) printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; } - mei_base_address = res->base; + mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index cfdea7c979..029da9fb35 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -47,7 +47,11 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else #define DEFAULT_RCBA 0xfed1c000 +#endif #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index cb5699e713..cf3b14ef90 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -66,7 +66,7 @@ static void sata_init(struct device *dev) /* AHCI */ if (sata_mode == 0) { - u32 abar; + u8 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -100,8 +100,8 @@ static void sata_init(struct device *dev) ((config->sata_port_map ^ 0x3f) << 24) | 0x183); /* Initialize AHCI memory-mapped space */ - abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %08X\n", abar); + abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 9850fee30d..b76963fdb1 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -66,8 +66,9 @@ static void usb_ehci_init(struct device *dev) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Number of ports and companion controllers. */ - reg32 = read32(res->base + 4); - write32(res->base + 4, (reg32 & 0xfff00000) | 3); + reg32 = read32((void *)(uintptr_t)(res->base + 4)); + write32((void *)(uintptr_t)(res->base + 4), + (reg32 & 0xfff00000) | 3); } /* Restore protection. */ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 3f22bc736f..d6ab01a545 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -199,7 +199,7 @@ enum { static u8 readb_(const void *addr) { - u8 v = read8((unsigned long)addr); + u8 v = read8(addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -207,7 +207,7 @@ static u8 readb_(const void *addr) static u16 readw_(const void *addr) { - u16 v = read16((unsigned long)addr); + u16 v = read16(addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -215,41 +215,41 @@ static u16 readw_(const void *addr) static u32 readl_(const void *addr) { - u32 v = read32((unsigned long)addr); + u32 v = read32(addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; } -static void writeb_(u8 b, const void *addr) +static void writeb_(u8 b, void *addr) { - write8((unsigned long)addr, b); + write8(addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } -static void writew_(u16 b, const void *addr) +static void writew_(u16 b, void *addr) { - write16((unsigned long)addr, b); + write16(addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } -static void writel_(u32 b, const void *addr) +static void writel_(u32 b, void *addr) { - write32((unsigned long)addr, b); + write32(addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ -#define readb_(a) read8((uint32_t)a) -#define readw_(a) read16((uint32_t)a) -#define readl_(a) read32((uint32_t)a) -#define writeb_(val, addr) write8((uint32_t)addr, val) -#define writew_(val, addr) write16((uint32_t)addr, val) -#define writel_(val, addr) write32((uint32_t)addr, val) +#define readb_(a) read8(a) +#define readw_(a) read16(a) +#define readl_(a) read32(a) +#define writeb_(val, addr) write8(addr, val) +#define writew_(val, addr) write16(addr, val) +#define writel_(val, addr) write32(addr, val) #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index b5b77efa14..22bb15038b 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -242,7 +242,7 @@ static void lpc_init(struct device *dev) value |= (1 << 8)|(1<<7); value |= (6 << 0)|(1<<13)|(1<<11); pci_write_config32(dev, 0xd0, value); - setup_ioapic(IO_APIC_ADDR, 0); // don't rename IO APIC ID + setup_ioapic(VIO_APIC_VADDR, 0); // don't rename IO APIC ID /* disable reset timer */ pci_write_config8(dev, 0xd4, 0x02); diff --git a/src/southbridge/intel/esb6300/pic.c b/src/southbridge/intel/esb6300/pic.c index e3fc2b2048..c453ca32bd 100644 --- a/src/southbridge/intel/esb6300/pic.c +++ b/src/southbridge/intel/esb6300/pic.c @@ -23,7 +23,7 @@ static void pic_init(struct device *dev) pci_write_config8(dev, 0x3c, 0xff); /* Setup the ioapic */ - clear_ioapic(IO_APIC_ADDR + 0x10000); + clear_ioapic((void *)(IO_APIC_ADDR + 0x10000)); } static void pic_read_resources(device_t dev) diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c index 7a280c56e2..f4988d6ec3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/azalia.c +++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c @@ -34,7 +34,7 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static int set_bits(u32 port, u32 mask, u32 val) +static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -63,7 +63,7 @@ static int set_bits(u32 port, u32 mask, u32 val) return 0; } -static int codec_detect(u32 base) +static int codec_detect(u8 *base) { u8 reg8; @@ -72,7 +72,8 @@ static int codec_detect(u32 base) goto no_codec; /* Write back the value once reset bit is set. */ - write16(base + 0x0, read16(base + 0x0)); + write16(base + 0x0, + read16(base + 0x0)); /* Read in Codec location (BAR + 0xe)[2..0]*/ reg8 = read8(base + 0xe); @@ -118,7 +119,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) * no response would imply that the codec is non-operative */ -static int wait_for_ready(u32 base) +static int wait_for_ready(u8 *base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -126,7 +127,7 @@ static int wait_for_ready(u32 base) int timeout = 50; while(timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -141,7 +142,7 @@ static int wait_for_ready(u32 base) * is non-operative */ -static int wait_for_valid(u32 base) +static int wait_for_valid(u8 *base) { u32 reg32; @@ -165,7 +166,7 @@ static int wait_for_valid(u32 base) return -1; } -static void codec_init(struct device *dev, u32 base, int addr) +static void codec_init(struct device *dev, u8 *base, int addr) { u32 reg32; const u32 *verb; @@ -213,7 +214,7 @@ static void codec_init(struct device *dev, u32 base, int addr) printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } -static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; for (i = 3; i >= 0; i--) { @@ -234,7 +235,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void azalia_init(struct device *dev) { - u32 base; + u8 *base; struct resource *res; u32 codec_mask; u8 reg8; @@ -248,7 +249,7 @@ static void azalia_init(struct device *dev) // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? - base = (u32)res->base; + base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); if (RCBA32(0x2030) & (1 << 31)) { diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 9b3e97aa34..c42a79733a 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -58,7 +58,7 @@ static void enable_port80_on_lpc(void) pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); /* Enable port 80 POST on LPC */ - pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); + pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); u32 reg32 = *gcs; reg32 = reg32 & ~0x04; diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c index c89395dcf5..7b630f4143 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_init.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c @@ -143,7 +143,7 @@ static void sandybridge_setup_bars(void) { /* Setting up Southbridge. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 5326eb5402..bcaeeeb232 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -63,7 +63,7 @@ static const char *me_bios_path_values[] = { #endif /* MMIO base address for MEI interface */ -static u32 mei_base_address; +static u32 *mei_base_address; #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -105,7 +105,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) static inline void mei_read_dword_ptr(void *ptr, int offset) { - u32 dword = read32(mei_base_address + offset); + u32 dword = read32(mei_base_address + (offset/sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } @@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); + write32(mei_base_address + (offset/sizeof(u32)), dword); mei_dump(ptr, dword, offset, "WRITE"); } @@ -144,13 +144,13 @@ static inline void read_me_csr(struct mei_csr *csr) static inline void write_cb(u32 dword) { - write32(mei_base_address + MEI_H_CB_WW, dword); + write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { - u32 dword = read32(mei_base_address + MEI_ME_CB_RW); + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); return dword; } @@ -500,11 +500,11 @@ static void intel_me7_finalize_smm(void) struct me_hfs hfs; u32 reg32; - mei_base_address = - pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + mei_base_address = (u32 *) + (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == 0xfffffff0) + if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ @@ -626,7 +626,7 @@ static int intel_mei_setup(device_t dev) printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; } - mei_base_address = res->base; + mei_base_address = res2mmio(res, 0, 0); /* Ensure Memory and Bus Master bits are set */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index d673ac783c..9af5f9386c 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -64,7 +64,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data); #endif /* MMIO base address for MEI interface */ -static u32 mei_base_address; +static u32 *mei_base_address; #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) static inline void mei_read_dword_ptr(void *ptr, int offset) { - u32 dword = read32(mei_base_address + offset); + u32 dword = read32(mei_base_address + (offset/sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } @@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); + write32(mei_base_address + (offset/sizeof(u32)), dword); mei_dump(ptr, dword, offset, "WRITE"); } @@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr) static inline void write_cb(u32 dword) { - write32(mei_base_address + MEI_H_CB_WW, dword); + write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { - u32 dword = read32(mei_base_address + MEI_ME_CB_RW); + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); return dword; } @@ -494,11 +494,11 @@ void intel_me8_finalize_smm(void) struct me_hfs hfs; u32 reg32; - mei_base_address = - pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + mei_base_address = (u32 *) + (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == 0xfffffff0) + if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ @@ -613,7 +613,7 @@ static int intel_mei_setup(device_t dev) printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; } - mei_base_address = res->base; + mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index a06ca7421e..c1e9b71810 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -48,7 +48,11 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0400 +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else #define DEFAULT_RCBA 0xfed1c000 +#endif #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 591bdbc3d0..ff0e20bfd8 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -57,7 +57,7 @@ static void sata_init(struct device *dev) reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); } else if(config->sata_ahci) { - u32 abar; + u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -66,12 +66,12 @@ static void sata_init(struct device *dev) pci_write_config8(dev, INTR_LN, 0x0a); /* Initialize AHCI memory-mapped space */ - abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %08X\n", abar); + abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Enable AHCI Mode */ - reg32 = read32(abar + 0x04); + reg32 = read32(abar + 0x01); reg32 |= (1 << 31); - write32(abar + 0x04, reg32); + write32(abar + 0x01, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 844f4b8492..e4e7071cd1 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -34,15 +34,15 @@ static void rangeley_setup_bars(void) { /* Setting up Southbridge. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(LPC_BDF, RCBA, DEFAULT_RCBA | RCBA_ENABLE); + pci_write_config32(LPC_BDF, RCBA, (uintptr_t)DEFAULT_RCBA | RCBA_ENABLE); pci_write_config32(LPC_BDF, ABASE, DEFAULT_ABASE | SET_BAR_ENABLE); pci_write_config32(LPC_BDF, PBASE, DEFAULT_PBASE | SET_BAR_ENABLE); printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, "Disabling Watchdog timer..."); /* Disable the watchdog reboot and turn off the watchdog timer */ - write8(DEFAULT_PBASE + PMC_CFG, read8(DEFAULT_PBASE + PMC_CFG) | - NO_REBOOT); // disable reboot on timer trigger + write8((void *)(DEFAULT_PBASE + PMC_CFG), + read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT); // disable watchdog timer @@ -54,7 +54,7 @@ static void reset_rtc(void) { uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0; - uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1); + uint32_t gen_pmcon1 = read32((void *)(pbase + GEN_PMCON1)); int rtc_failed = !!(gen_pmcon1 & RPS); if (rtc_failed) { @@ -63,7 +63,8 @@ static void reset_rtc(void) coreboot_dmi_date); /* Clear the power failure flag */ - write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS); + write32((void *)(DEFAULT_PBASE + GEN_PMCON1), + gen_pmcon1 & ~RPS); } cmos_init(rtc_failed); diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c index 8569b967d4..6ea9c2e7e5 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.c +++ b/src/southbridge/intel/fsp_rangeley/gpio.c @@ -30,7 +30,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) { u16 gpiobase = pci_read_config16(SOC_LPC_DEV, GBASE) & ~0xf; - u32 cfiobase = pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf; + u32 *cfiobase = (u32 *)(pci_read_config32(SOC_LPC_DEV, IOBASE) & ~0xf); u32 cfio_cnt = 0; @@ -67,30 +67,30 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) /* GPIO PAD settings */ /* CFIO Core Well Set 1 */ if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) { - write32(cfiobase + 0x0700, (u32)0x01001002); + write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002); for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0)) continue; - write32(cfiobase + CFIO_PAD_CONF0 + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0); - write32(cfiobase + CFIO_PAD_CONF1 + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1); - write32(cfiobase + CFIO_PAD_VAL + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_val); - write32(cfiobase + CFIO_PAD_DFT + (16*cfio_cnt), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft); + write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0); + write32(cfiobase + ((CFIO_PAD_CONF1 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_1); + write32(cfiobase + ((CFIO_PAD_VAL + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_val); + write32(cfiobase + ((CFIO_PAD_DFT + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_dft); } - write32(cfiobase + 0x0700, (u32)0x01041002); + write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01041002); } /* CFIO SUS Well Set 1 */ if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) { - write32(cfiobase + 0x1700, (u32)0x01001002); + write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002); for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0)) continue; - write32(cfiobase + CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0); - write32(cfiobase + CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1); - write32(cfiobase + CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val); - write32(cfiobase + CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft); + write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0); + write32(cfiobase + ((CFIO_PAD_CONF1 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_1); + write32(cfiobase + ((CFIO_PAD_VAL + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_val); + write32(cfiobase + ((CFIO_PAD_DFT + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_dft); } - write32(cfiobase + 0x1700, (u32)0x01041002); + write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01041002); } } diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 9644067971..8f2967048a 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -52,7 +52,7 @@ static void soc_enable_apic(struct device *dev) u32 reg32; volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - u32 ilb_base = pci_read_config32(dev, IBASE) & ~0x0f; + u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f); /* * Enable ACPI I/O and power management. @@ -91,9 +91,9 @@ static void soc_enable_apic(struct device *dev) static void soc_enable_serial_irqs(struct device *dev) { - u32 ibase; + u8 *ibase; - ibase = pci_read_config32(dev, IBASE) & ~0xF; + ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); /* Set packet length and toggle silent mode bit for one frame. */ write8(ibase + ILB_SERIRQ_CNTL, (1 << 7)); @@ -206,10 +206,10 @@ static void soc_pirq_init(device_t dev) { int i, j; int pirq; - const u32 ibase = pci_read_config32(dev, IBASE) & ~0xF; - const unsigned long pr_base = ibase + 0x08; - const unsigned long ir_base = ibase + 0x20; - const unsigned long actl = ibase; + u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); + u8 *pr_base = ibase + 0x08; + u16 *ir_base = (u16 *)(ibase + 0x20); + u32 *actl = (u32 *)ibase; const struct rangeley_irq_route *ir = &global_rangeley_irq_route; /* Set up the PIRQ PIC routing based on static config. */ @@ -226,7 +226,7 @@ static void soc_pirq_init(device_t dev) printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n" "Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n"); for (i = 0; i < NUM_OF_PCI_DEVS; i++) { - write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]); + write16(ir_base + i, ir->pcidev[i]); /* If the entry is more than just 0, print it out */ if(ir->pcidev[i]) { @@ -293,10 +293,10 @@ static void soc_power_options(device_t dev) /* Disable the HPET, Clear the counter, and re-enable it. */ static void enable_hpet(void) { - write8(HPET_GCFG, 0x00); - write32(HPET_MCV, 0x00000000); - write32(HPET_MCV + 0x04, 0x00000000); - write8(HPET_GCFG, 0x01); + write8((u8 *)HPET_GCFG, 0x00); + write32((u32 *)HPET_MCV, 0x00000000); + write32((u32 *)(HPET_MCV + 0x04), 0x00000000); + write8((u8 *)HPET_GCFG, 0x01); } static void soc_disable_smm_only_flashing(struct device *dev) diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index a668815fe8..e6b4f62d7e 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -42,7 +42,7 @@ void main(FSP_INFO_HEADER *fsp_info_header) { uint32_t fd_mask = 0; - uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS; + uint32_t *func_dis = (uint32_t *)(DEFAULT_PBASE + PBASE_FUNC_DIS); /* * Do not use the Serial Console before it is setup. diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index f672e4c428..4648ac7467 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -32,7 +32,7 @@ static void sata_init(struct device *dev) { u32 reg32; u16 reg16; - u32 abar; + u32 *abar; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -74,13 +74,13 @@ static void sata_init(struct device *dev) pci_write_config16(dev, SATA_MAP, reg16); /* Initialize AHCI memory-mapped space */ - abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %08X\n", abar); + abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Enable AHCI Mode */ - reg32 = read32(abar + 0x04); + reg32 = read32(abar + 0x01); reg32 |= (1 << 31); - write32(abar + 0x04, reg32); + write32(abar + 0x01, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); } diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 6db4b11da3..f1b1781afc 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -43,7 +43,11 @@ /* Southbridge internal device MEM BARs (Set to match FSP settings) */ #define DEFAULT_IBASE 0xfed08000 #define DEFAULT_PBASE 0xfed03000 +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else #define DEFAULT_RCBA 0xfed1c000 +#endif #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index ee22019ade..b813d0763e 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -231,7 +231,7 @@ enum { static u8 readb_(const void *addr) { - u8 v = read8((unsigned long)addr); + u8 v = read8(addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -239,7 +239,7 @@ static u8 readb_(const void *addr) static u16 readw_(const void *addr) { - u16 v = read16((unsigned long)addr); + u16 v = read16(addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -247,7 +247,7 @@ static u16 readw_(const void *addr) static u32 readl_(const void *addr) { - u32 v = read32((unsigned long)addr); + u32 v = read32(addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -255,14 +255,14 @@ static u32 readl_(const void *addr) static void writeb_(u8 b, const void *addr) { - write8((unsigned long)addr, b); + write8(addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } static void writew_(u16 b, const void *addr) { - write16((unsigned long)addr, b); + write16(addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } @@ -276,12 +276,12 @@ static void writel_(u32 b, const void *addr) #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ -#define readb_(a) read8((uint32_t)a) -#define readw_(a) read16((uint32_t)a) -#define readl_(a) read32((uint32_t)a) -#define writeb_(val, addr) write8((uint32_t)addr, val) -#define writew_(val, addr) write16((uint32_t)addr, val) -#define writel_(val, addr) write32((uint32_t)addr, val) +#define readb_(a) read8(a) +#define readw_(a) read16(a) +#define readl_(a) read32(a) +#define writeb_(val, addr) write8(addr, val) +#define writew_(val, addr) write16(addr, val) +#define writel_(val, addr) write32(addr, val) #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index ba74f30748..737ec65a5b 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -358,7 +358,7 @@ static void lpc_init(struct device *dev) // TODO this code sets int 0 of the IOAPIC in Virtual Wire Mode // (register 0x10/0x11) while the old code used int 1 (register 0x12) // ... Why? - setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IOAPIC ID + setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IOAPIC ID /* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */ pci_write_config32(dev, 0xd0, 0x00000000); diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 11519c1fb3..aece45232d 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -103,13 +103,13 @@ static void i82801ax_enable_ioapic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - set_ioapic_id(IO_APIC_ADDR, 0x02); + set_ioapic_id(VIO_APIC_VADDR, 0x02); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void i82801ax_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 278d65c3c1..ee0b52109d 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -104,13 +104,13 @@ static void i82801bx_enable_ioapic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - set_ioapic_id(IO_APIC_ADDR, 0x02); + set_ioapic_id(VIO_APIC_VADDR, 0x02); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void i82801bx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index f6c33b7feb..22671c3de3 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -41,13 +41,13 @@ static void i82801cx_enable_ioapic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - set_ioapic_id(IO_APIC_ADDR, 0x02); + set_ioapic_id(VIO_APIC_VADDR, 0x02); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } // This is how interrupts are received from the Super I/O chip diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 1b23fad832..83d617897e 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -67,13 +67,13 @@ static void i82801dx_enable_ioapic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - set_ioapic_id(IO_APIC_ADDR, 0x02); + set_ioapic_id(VIO_APIC_VADDR, 0x02); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void i82801dx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 1823e65cf4..0a2f6e3d11 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -281,7 +281,7 @@ static void lpc_init(struct device *dev) i82801ex_general_cntl(dev); /* IO APIC initialization. */ - setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. + setup_ioapic(VIO_APIC_VADDR, 0); // Don't rename IO APIC ID. i82801ex_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index f6628e7c95..3d3d73edc7 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -34,7 +34,7 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static int set_bits(u32 port, u32 mask, u32 val) +static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -63,7 +63,7 @@ static int set_bits(u32 port, u32 mask, u32 val) return 0; } -static int codec_detect(u32 base) +static int codec_detect(u8 *base) { u32 reg32; @@ -114,7 +114,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) * no response would imply that the codec is non-operative */ -static int wait_for_ready(u32 base) +static int wait_for_ready(u8 *base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -122,7 +122,7 @@ static int wait_for_ready(u32 base) int timeout = 50; while(timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -137,7 +137,7 @@ static int wait_for_ready(u32 base) * is non-operative */ -static int wait_for_valid(u32 base) +static int wait_for_valid(u8 *base) { u32 reg32; @@ -161,7 +161,7 @@ static int wait_for_valid(u32 base) return -1; } -static void codec_init(struct device *dev, u32 base, int addr) +static void codec_init(struct device *dev, u8 *base, int addr) { u32 reg32; const u32 *verb; @@ -205,7 +205,7 @@ static void codec_init(struct device *dev, u32 base, int addr) printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } -static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; for (i = 2; i >= 0; i--) { @@ -216,7 +216,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void azalia_init(struct device *dev) { - u32 base; + u8 *base; struct resource *res; u32 codec_mask; u8 reg8; @@ -297,7 +297,7 @@ static void azalia_init(struct device *dev) // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? - base = (u32)res->base; + base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); codec_mask = codec_detect(base); diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index d8e03b7639..5954e6c3b5 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -53,7 +53,7 @@ static void bootblock_southbridge_init(void) enable_spi_prefetch(); /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); /* Enable upper 128bytes of CMOS */ RCBA32(0x3400) = (1 << 2); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index ee13b7d99a..462484100d 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -32,7 +32,11 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else #define DEFAULT_RCBA 0xfed1c000 +#endif #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 6b9d11e19b..cbc010605b 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -53,13 +53,13 @@ static void i82801gx_enable_ioapic(struct device *dev) /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(IO_APIC_ADDR, 0x02); + set_ioapic_id(VIO_APIC_VADDR, 0x02); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void i82801gx_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index bb176c77a1..161190b30b 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -29,7 +29,7 @@ static void usb_ehci_init(struct device *dev) { struct resource *res; - u32 base; + u8 *base; u32 reg32; u8 reg8; @@ -50,7 +50,7 @@ static void usb_ehci_init(struct device *dev) /* Clear any pending port changes */ res = find_resource(dev, 0x10); - base = res->base; + base = res2mmio(res, 0, 0); reg32 = read32(base + 0x24) | (1 << 2); write32(base + 0x24, reg32); diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index 3d9df6dd16..bca109a354 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -87,7 +87,7 @@ void i82801ix_dmi_setup(void) RCBA8(RCBA_ULD + 3) = 1; RCBA8(RCBA_ULD + 2) = 1; /* Set target rcrb base address, i.e. DMIBAR. */ - RCBA32(RCBA_ULBA) = DEFAULT_DMIBAR; + RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR; /* Enable ASPM. */ if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) { diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index bd6548c6ba..1e3b517b1a 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -26,7 +26,7 @@ void i82801ix_early_init(void) const device_t d31f0 = PCI_DEV(0, 0x1f, 0); /* Set up RCBA. */ - pci_write_config32(d31f0, D31F0_RCBA, DEFAULT_RCBA | 1); + pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1); /* Set up PMBASE. */ pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index dd817b9b08..69c558dd06 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -35,7 +35,7 @@ typedef struct southbridge_intel_i82801ix_config config_t; -static int set_bits(u32 port, u32 mask, u32 val) +static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -64,7 +64,7 @@ static int set_bits(u32 port, u32 mask, u32 val) return 0; } -static int codec_detect(u32 base) +static int codec_detect(u8 *base) { u32 reg32; @@ -115,7 +115,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) * no response would imply that the codec is non-operative */ -static int wait_for_ready(u32 base) +static int wait_for_ready(u8 *base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -123,7 +123,7 @@ static int wait_for_ready(u32 base) int timeout = 50; while(timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -138,7 +138,7 @@ static int wait_for_ready(u32 base) * is non-operative */ -static int wait_for_valid(u32 base) +static int wait_for_valid(u8 *base) { u32 reg32; @@ -162,7 +162,7 @@ static int wait_for_valid(u32 base) return -1; } -static void codec_init(struct device *dev, u32 base, int addr) +static void codec_init(struct device *dev, u8 *base, int addr) { u32 reg32; const u32 *verb; @@ -206,7 +206,7 @@ static void codec_init(struct device *dev, u32 base, int addr) printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } -static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; for (i = 2; i >= 0; i--) { @@ -227,7 +227,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void azalia_init(struct device *dev) { - u32 base; + u8 *base; struct resource *res; u32 codec_mask; u8 reg8; @@ -281,7 +281,7 @@ static void azalia_init(struct device *dev) // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? - base = (u32)res->base; + base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); codec_mask = codec_detect(base); diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index d8dc077673..10b27179ca 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -27,8 +27,13 @@ #endif #endif -#define DEFAULT_TBAR 0xfed1b000 +#define DEFAULT_TBAR ((u8 *)0xfed1b000) +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else #define DEFAULT_RCBA 0xfed1c000 +#endif + #ifdef CONFIG_BOARD_EMULATION_QEMU_X86_Q35 /* * Qemu has the fw_cfg interface at 0x510. Move the pmbase to a diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 6038eff114..0ba33d6759 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -62,7 +62,7 @@ static void i82801ix_enable_apic(struct device *dev) *ioapic_index = 0x01; *ioapic_data = reg32; - setup_ioapic(IO_APIC_ADDR, 2); /* ICH7 code uses id 2. */ + setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */ } static void i82801ix_enable_serial_irqs(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index 10c8a2bd15..f65eba26b4 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -36,8 +36,8 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, u32 reg32; /* Initialize AHCI memory-mapped space */ - const u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %08X\n", abar); + u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Set AHCI access mode. No other ABAR registers should be accessed before this. */ @@ -67,7 +67,7 @@ static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, for (i = 0; i < 6; ++i) { if (((i == 2) || (i == 3)) && is_mobile) continue; - const u32 addr = abar + 0x118 + (i * 0x80); + u8 *addr = abar + 0x118 + (i * 0x80); write32(addr, read32(addr)); } } diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index 3245a27962..84afe93b54 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -34,7 +34,7 @@ static void thermal_init(struct device *dev) u8 reg8; u32 reg32; - pci_write_config32(dev, 0x10, DEFAULT_TBAR); + pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR); reg32 = pci_read_config32(dev, 0x04); pci_write_config32(dev, 0x04, reg32 | (1 << 1)); diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 314a1b1d19..2275c7aee4 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -33,7 +33,7 @@ #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) -static int set_bits(u32 port, u32 mask, u32 val) +static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -62,7 +62,7 @@ static int set_bits(u32 port, u32 mask, u32 val) return 0; } -static int codec_detect(u32 base) +static int codec_detect(u8 *base) { u8 reg8; @@ -71,7 +71,8 @@ static int codec_detect(u32 base) goto no_codec; /* Write back the value once reset bit is set. */ - write16(base + 0x0, read16(base + 0x0)); + write16(base + 0x0, + read16(base + 0x0)); /* Read in Codec location (BAR + 0xe)[2..0]*/ reg8 = read8(base + 0xe); @@ -112,14 +113,14 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) * no response would imply that the codec is non-operative */ -static int wait_for_ready(u32 base) +static int wait_for_ready(u8 *base) { /* Use a 1msec timeout */ int timeout = 1000; while(timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -134,7 +135,7 @@ static int wait_for_ready(u32 base) * is non-operative */ -static int wait_for_valid(u32 base) +static int wait_for_valid(u8 *base) { u32 reg32; @@ -157,7 +158,7 @@ static int wait_for_valid(u32 base) return -1; } -static void codec_init(struct device *dev, u32 base, int addr) +static void codec_init(struct device *dev, u8 *base, int addr) { u32 reg32; const u32 *verb; @@ -205,7 +206,7 @@ static void codec_init(struct device *dev, u32 base, int addr) printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } -static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; for (i = 3; i >= 0; i--) { @@ -226,7 +227,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void azalia_init(struct device *dev) { - u32 base; + u8 *base; struct resource *res; u32 codec_mask; u8 reg8; @@ -240,7 +241,7 @@ static void azalia_init(struct device *dev) // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? - base = (u32)res->base; + base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); if (RCBA32(0x2030) & (1 << 31)) { diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index d23749e513..e765943b24 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -43,11 +43,12 @@ void early_thermal_init(void) /* Perform init. */ /* Configure TJmax. */ msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6); + write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6); /* Northbridge temperature slope and offset. */ - write16(0x40000016, 0x7746); + write16((u16 *)0x40000016, 0x7746); /* Enable thermal data reporting, processor, PCH and northbridge. */ - write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0); + write16((u16 *)0x4000001a, + (read16((u16 *)0x4000001a) & ~0xf) | 0x10f0); /* Disable temporary BAR. */ pci_write_config32(dev, 0x40, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 212471136d..db73b0add8 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -59,16 +59,16 @@ static void pch_enable_ioapic(struct device *dev) /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(IO_APIC_ADDR, 0x01); + set_ioapic_id(VIO_APIC_VADDR, 0x01); /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read(IO_APIC_ADDR, 0x01); - io_apic_write(IO_APIC_ADDR, 0x01, reg32); + reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x01, reg32); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) @@ -394,7 +394,7 @@ static void enable_hpet(void) reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; - write32(0xfed00010, read32(0xfed00010) | 1); + write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); } static void enable_clock_gating(device_t dev) diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index f94b17fab9..9592b23c3a 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -63,7 +63,7 @@ static const char *me_bios_path_values[] = { #endif /* MMIO base address for MEI interface */ -static u32 mei_base_address; +static u32 *mei_base_address; #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -105,7 +105,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) static inline void mei_read_dword_ptr(void *ptr, int offset) { - u32 dword = read32(mei_base_address + offset); + u32 dword = read32(mei_base_address + (offset/sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } @@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); + write32(mei_base_address + (offset/sizeof(u32)), dword); mei_dump(ptr, dword, offset, "WRITE"); } @@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr) static inline void write_cb(u32 dword) { - write32(mei_base_address + MEI_H_CB_WW, dword); + write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { - u32 dword = read32(mei_base_address + MEI_ME_CB_RW); + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); return dword; } @@ -382,11 +382,11 @@ static void intel_me7_finalize_smm(void) struct me_hfs hfs; u32 reg32; - mei_base_address = - pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + mei_base_address = (u32 *) + (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == 0xfffffff0) + if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ @@ -508,7 +508,7 @@ static int intel_mei_setup(device_t dev) printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; } - mei_base_address = res->base; + mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index bd94689e78..12e9345bf7 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -48,7 +48,11 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else #define DEFAULT_RCBA 0xfed1c000 +#endif #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 5f3c4d3aa5..c8450ad447 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -67,7 +67,7 @@ static void sata_init(struct device *dev) if (sata_mode == 0) { /* AHCI */ - u32 abar; + u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -103,8 +103,8 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, 0x00590200); /* Initialize AHCI memory-mapped space */ - abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %08X\n", abar); + abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS @@ -118,16 +118,16 @@ static void sata_init(struct device *dev) write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); - (void)read32(abar + 0x0c); /* Read back 1 */ - (void)read32(abar + 0x0c); /* Read back 2 */ + (void)read32(abar + 0x03); /* Read back 1 */ + (void)read32(abar + 0x03); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended) */ - reg32 = read32(abar + 0x24); + reg32 = read32(abar + 0x09); reg32 &= ~0x00000002; - write32(abar + 0x24, reg32); + write32(abar + 0x09, reg32); /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0xa0); + reg32 = read32(abar + 0x28); reg32 &= ~0x00000005; - write32(abar + 0xa0, reg32); + write32(abar + 0x28, reg32); } else { /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index fa39626bf0..c684955441 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -28,21 +28,22 @@ static void thermal_init(struct device *dev) { struct resource *res; - + u8 *base; printk(BIOS_DEBUG, "Thermal init start.\n"); res = find_resource(dev, 0x10); if (!res) return; - write32(res->base + 4, 0x3a2b); - write8(res->base + 0xe, 0x40); - write16(res->base + 0x56, 0xffff); - write16(res->base + 0x64, 0xffff); - write16(res->base + 0x66, 0xffff); - write16(res->base + 0x68, 0xfa); + base = res2mmio(res, 0, 0); + write32(base + 4, 0x3a2b); + write8(base + 0xe, 0x40); + write16(base + 0x56, 0xffff); + write16(base + 0x64, 0xffff); + write16(base + 0x66, 0xffff); + write16(base + 0x68, 0xfa); - write8(res->base + 1, 0xb8); + write8(base + 1, 0xb8); printk(BIOS_DEBUG, "Thermal init done.\n"); } diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 868a06843c..6a48d13662 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -60,8 +60,9 @@ static void usb_ehci_init(struct device *dev) res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Number of ports and companion controllers. */ - reg32 = read32(res->base + 4); - write32(res->base + 4, (reg32 & 0xfff00000) | 2); + reg32 = read32((u32 *)(uintptr_t)(res->base + 4)); + write32((u32 *)(uintptr_t)(res->base + 4), + (reg32 & 0xfff00000) | 2); } /* Restore protection. */ diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index be056be493..168b8d22a2 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -30,7 +30,7 @@ #include "pch.h" #include "hda_verb.h" -static void codecs_init(u32 base, u32 codec_mask) +static void codecs_init(u8 *base, u32 codec_mask) { int i; @@ -46,7 +46,7 @@ static void codecs_init(u32 base, u32 codec_mask) hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); } -static void azalia_pch_init(struct device *dev, u32 base) +static void azalia_pch_init(struct device *dev, u8 *base) { u8 reg8; u16 reg16; @@ -131,7 +131,7 @@ static void azalia_pch_init(struct device *dev, u32 base) static void azalia_init(struct device *dev) { - u32 base; + u8 *base; struct resource *res; u32 codec_mask; u32 reg32; @@ -141,8 +141,8 @@ static void azalia_init(struct device *dev) if (!res) return; - base = (u32)res->base; - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base); /* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 40c6bb8c46..9d9e7b3a8c 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -53,7 +53,7 @@ static void map_rcba(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); + pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); } static void enable_port80_on_lpc(void) diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 5378428e83..eabf548d7a 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -52,7 +52,7 @@ int pch_is_lp(void) static void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ - pci_write_config32(PCH_LPC_DEV, RCBA, DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 424deb52bb..8f38ccec60 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -28,7 +28,7 @@ /** * Set bits in a register and wait for status */ -static int set_bits(u32 port, u32 mask, u32 val) +static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -60,7 +60,7 @@ static int set_bits(u32 port, u32 mask, u32 val) /** * Probe for supported codecs */ -int hda_codec_detect(u32 base) +int hda_codec_detect(u8 *base) { u8 reg8; @@ -91,7 +91,7 @@ no_codec: * Wait 50usec for the codec to indicate it is ready * no response would imply that the codec is non-operative */ -static int hda_wait_for_ready(u32 base) +static int hda_wait_for_ready(u8 *base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -113,7 +113,7 @@ static int hda_wait_for_ready(u32 base) * the previous command. No response would imply that the code * is non-operative */ -static int hda_wait_for_valid(u32 base) +static int hda_wait_for_valid(u8 *base) { u32 reg32; @@ -185,7 +185,7 @@ static u32 hda_find_verb(u32 verb_table_bytes, /** * Write a supplied verb table */ -int hda_codec_write(u32 base, u32 size, const u32 *data) +int hda_codec_write(u8 *base, u32 size, const u32 *data) { int i; @@ -205,7 +205,7 @@ int hda_codec_write(u32 base, u32 size, const u32 *data) /** * Initialize codec, then find the verb table and write it */ -int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data) +int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data) { const u32 *verb; u32 reg32, size; diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h index 8b3d27e1c2..52c1468c06 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.h +++ b/src/southbridge/intel/lynxpoint/hda_verb.h @@ -30,8 +30,8 @@ #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) -int hda_codec_detect(u32 base); -int hda_codec_write(u32 base, u32 size, const u32 *data); -int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data); +int hda_codec_detect(u8 *base); +int hda_codec_write(u8 *base, u32 size, const u32 *data); +int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data); #endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 563cb0a26d..d753bea776 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -57,22 +57,22 @@ static void pch_enable_ioapic(struct device *dev) /* Enable ACPI I/O range decode */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(IO_APIC_ADDR, 0x02); + set_ioapic_id(VIO_APIC_VADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read(IO_APIC_ADDR, 0x01); + reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); if (pch_is_lp()) { /* PCH-LP has 39 redirection entries */ reg32 &= ~0x00ff0000; reg32 |= 0x00270000; } - io_apic_write(IO_APIC_ADDR, 0x01, reg32); + io_apic_write(VIO_APIC_VADDR, 0x01, reg32); /* * Select Boot Configuration register (0x03) and * use Processor System Bus (0x01) to deliver interrupts. */ - io_apic_write(IO_APIC_ADDR, 0x03, 0x01); + io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void pch_enable_serial_irqs(struct device *dev) @@ -608,9 +608,9 @@ static void pch_lpc_add_mmio_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* RCBA */ - if (DEFAULT_RCBA < default_decode_base) { + if ((uintptr_t)DEFAULT_RCBA < default_decode_base) { res = new_resource(dev, RCBA); - res->base = DEFAULT_RCBA; + res->base = (resource_t)(uintptr_t)DEFAULT_RCBA; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 9670bbb659..e32a2d9be3 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -61,7 +61,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); #endif /* MMIO base address for MEI interface */ -static u32 mei_base_address; +static u32 *mei_base_address; void intel_me_mbp_clear(device_t dev); #if CONFIG_DEBUG_INTEL_ME @@ -104,7 +104,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) static inline void mei_read_dword_ptr(void *ptr, int offset) { - u32 dword = read32(mei_base_address + offset); + u32 dword = read32(mei_base_address + (offset/sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } @@ -113,7 +113,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); + write32(mei_base_address + (offset/sizeof(u32)), dword); mei_dump(ptr, dword, offset, "WRITE"); } @@ -141,13 +141,13 @@ static inline void read_me_csr(struct mei_csr *csr) static inline void write_cb(u32 dword) { - write32(mei_base_address + MEI_H_CB_WW, dword); + write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { - u32 dword = read32(mei_base_address + MEI_ME_CB_RW); + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); return dword; } @@ -577,11 +577,11 @@ void intel_me_finalize_smm(void) struct me_hfs hfs; u32 reg32; - mei_base_address = - pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + mei_base_address = (u32 *) + (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == 0xfffffff0) + if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; #if CONFIG_ME_MBP_CLEAR_LATE @@ -745,7 +745,7 @@ static int intel_mei_setup(device_t dev) printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; } - mei_base_address = res->base; + mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9b5cb6f160..5ee7cd973b 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -83,7 +83,11 @@ #endif #define HPET_ADDR 0xfed00000 +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else #define DEFAULT_RCBA 0xfed1c000 +#endif #ifndef __ACPI__ diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 43a99c8b66..89a72f4fcc 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -96,7 +96,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } else if(config->sata_ahci) { - u32 abar; + u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -156,8 +156,8 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ - abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %08X\n", abar); + abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS @@ -166,11 +166,11 @@ static void sata_init(struct device *dev) reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY write32(abar + 0x00, reg32); /* PI (Ports implemented) */ - write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + write32(abar + 0x03, config->sata_port_map); + (void) read32(abar + 0x03); /* Read back 1 */ + (void) read32(abar + 0x03); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x24); + reg32 = read32(abar + 0x09); /* Enable DEVSLP */ if (pch_is_lp()) { if (config->sata_devslp_disable) @@ -180,7 +180,7 @@ static void sata_init(struct device *dev) } else { reg32 &= ~0x00000002; } - write32(abar + 0x24, reg32); + write32(abar + 0x09, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 75edf5c9db..398895a2e9 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -32,9 +32,9 @@ /* Enable clock in PCI mode */ static void serialio_enable_clock(struct resource *bar0) { - u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK); + u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0)); reg32 |= SIO_REG_PPR_CLOCK_EN; - write32(bar0->base + SIO_REG_PPR_CLOCK, reg32); + write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32); } /* Put Serial IO D21:F0-F6 device into desired mode. */ @@ -85,22 +85,22 @@ static void serialio_d21_ltr(struct resource *bar0) u32 reg; /* 1. Program BAR0 + 808h[2] = 0b */ - reg = read32(bar0->base + SIO_REG_PPR_GEN); + reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0)); reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK; - write32(bar0->base + SIO_REG_PPR_GEN, reg); + write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg); /* 2. Program BAR0 + 804h[1:0] = 00b */ - reg = read32(bar0->base + SIO_REG_PPR_RST); + reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0)); reg &= ~SIO_REG_PPR_RST_ASSERT; - write32(bar0->base + SIO_REG_PPR_RST, reg); + write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg); /* 3. Program BAR0 + 804h[1:0] = 11b */ - reg = read32(bar0->base + SIO_REG_PPR_RST); + reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0)); reg |= SIO_REG_PPR_RST_ASSERT; - write32(bar0->base + SIO_REG_PPR_RST, reg); + write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg); /* 4. Program BAR0 + 814h[31:0] = 00000000h */ - write32(bar0->base + SIO_REG_AUTO_LTR, 0); + write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0); } /* Enable LTR Auto Mode for D23:F0. */ @@ -109,26 +109,26 @@ static void serialio_d23_ltr(struct resource *bar0) u32 reg; /* Program BAR0 + 1008h[2] = 1b */ - reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN); + reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0)); reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK; - write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg); + write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg); /* Program BAR0 + 1010h = 0x00000000 */ - write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0); + write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0); /* Program BAR0 + 3Ch[30] = 1b */ - reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12); + reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0)); reg |= SIO_REG_SDIO_PPR_CMD12_B30; - write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg); + write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg); } /* Select I2C voltage of 1.8V or 3.3V. */ static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage) { - u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN); + u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0)); reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK; reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage); - write32(bar0->base + SIO_REG_PPR_GEN, reg32); + write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32); } /* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */ diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 845129f7b2..7c35e673e8 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -64,13 +64,13 @@ void usb_ehci_disable(device_t dev) void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ) { u32 reg32; - u32 bar0_base; + u8 *bar0_base; u16 pwr_state; u16 pci_cmd; /* Check if the controller is disabled or not present */ - bar0_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - if (bar0_base == 0 || bar0_base == 0xffffffff) + bar0_base = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (bar0_base == 0 || bar0_base == (u8 *)0xffffffff) return; pci_cmd = pci_read_config32(dev, PCI_COMMAND); @@ -86,7 +86,7 @@ void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ) pci_write_config16(dev, EHCI_PWR_CTL_STS, new_state); /* Make sure memory bar is set */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar0_base); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)bar0_base); /* Make sure memory space is enabled */ pci_write_config16(dev, PCI_COMMAND, pci_cmd | diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 6c7bf046a8..3b8c23b27a 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -28,7 +28,7 @@ typedef struct southbridge_intel_lynxpoint_config config_t; -static u32 usb_xhci_mem_base(device_t dev) +static u8 *usb_xhci_mem_base(device_t dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -36,7 +36,7 @@ static u32 usb_xhci_mem_base(device_t dev) if (mem_base == 0 || mem_base == 0xffffffff) return 0; - return mem_base & ~0xf; + return (u8 *)(mem_base & ~0xf); } static int usb_xhci_port_count_usb3(device_t dev) @@ -46,7 +46,7 @@ static int usb_xhci_port_count_usb3(device_t dev) return 4; } else { /* LynxPoint-H can have 0, 2, 4, or 6 SS ports */ - u32 mem_base = usb_xhci_mem_base(dev); + u8 *mem_base = usb_xhci_mem_base(dev); u32 fus = read32(mem_base + XHCI_USB3FUS); fus >>= XHCI_USB3FUS_SS_SHIFT; fus &= XHCI_USB3FUS_SS_MASK; @@ -60,9 +60,9 @@ static int usb_xhci_port_count_usb3(device_t dev) return 0; } -static void usb_xhci_reset_status_usb3(u32 mem_base, int port) +static void usb_xhci_reset_status_usb3(u8 *mem_base, int port) { - u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); u32 status = read32(portsc); /* Do not set Port Enabled/Disabled field */ status &= ~XHCI_USB3_PORTSC_PED; @@ -71,9 +71,9 @@ static void usb_xhci_reset_status_usb3(u32 mem_base, int port) write32(portsc, status); } -static void usb_xhci_reset_port_usb3(u32 mem_base, int port) +static void usb_xhci_reset_port_usb3(u8 *mem_base, int port) { - u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR); } @@ -92,7 +92,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all) u32 status, port_disabled; int timeout, port; int port_count = usb_xhci_port_count_usb3(dev); - u32 mem_base = usb_xhci_mem_base(dev); + u8 *mem_base = usb_xhci_mem_base(dev); if (!mem_base || !port_count) return; @@ -121,7 +121,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all) /* Reset all requested ports */ for (port = 0; port < port_count; port++) { - u32 portsc = mem_base + XHCI_USB3_PORTSC(port); + u8 *portsc = mem_base + XHCI_USB3_PORTSC(port); /* Skip disabled ports */ if (port_disabled & (1 << port)) continue; @@ -164,7 +164,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) { u16 reg16; u32 reg32; - u32 mem_base = usb_xhci_mem_base(dev); + u8 *mem_base = usb_xhci_mem_base(dev); if (!mem_base || slp_typ < 3) return; @@ -295,7 +295,7 @@ static void usb_xhci_init(device_t dev) { u32 reg32; u16 reg16; - u32 mem_base = usb_xhci_mem_base(dev); + u8 *mem_base = usb_xhci_mem_base(dev); config_t *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ diff --git a/src/southbridge/intel/sch/audio.c b/src/southbridge/intel/sch/audio.c index 9c7793780a..83f5324f0e 100644 --- a/src/southbridge/intel/sch/audio.c +++ b/src/southbridge/intel/sch/audio.c @@ -32,7 +32,7 @@ typedef struct southbridge_intel_sch_config config_t; -static int set_bits(u32 port, u32 mask, u32 val) +static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -61,7 +61,7 @@ static int set_bits(u32 port, u32 mask, u32 val) return 0; } -static int codec_detect(u32 base) +static int codec_detect(u8 *base) { u32 reg32; int count; @@ -142,7 +142,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) * no response would imply that the codec is non-operative */ -static int wait_for_ready(u32 base) +static int wait_for_ready(u8 *base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -165,7 +165,7 @@ static int wait_for_ready(u32 base) * is non-operative */ -static int wait_for_valid(u32 base) +static int wait_for_valid(u8 *base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -190,7 +190,7 @@ static int wait_for_valid(u32 base) return -1; } -static void codec_init(struct device *dev, u32 base, int addr) +static void codec_init(struct device *dev, u8 *base, int addr) { u32 reg32; const u32 *verb; @@ -242,7 +242,7 @@ static void codec_init(struct device *dev, u32 base, int addr) printk(BIOS_DEBUG, "sch_audio: verb loaded.\n"); } -static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; @@ -254,7 +254,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void sch_audio_init(struct device *dev) { - u32 base; + u8 *base; struct resource *res; u32 codec_mask; u32 reg32; @@ -268,8 +268,8 @@ static void sch_audio_init(struct device *dev) // NOTE this will break as soon as the sch_audio get's a bar above // 4G. Is there anything we can do about it? - base = (u32) res->base; - printk(BIOS_DEBUG, "sch_audio: base = %08x\n", (u32) base); + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "sch_audio: base = %px\n", base); codec_mask = codec_detect(base); if (codec_mask) { |