diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-08-13 09:41:54 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-11-07 08:29:09 +0100 |
| commit | b1c8f81b25cd77056f653b9a7d5f24e65e40e655 (patch) | |
| tree | 8dfe6fb3fa920480d1c9294e65627453079e5bdb /src/southbridge/intel | |
| parent | 4dceba25af5ae025fb2592f478a0f29c0eca7fb5 (diff) | |
SMI: Change order of SMI_EN and PM1_EN init
This appears to fix an infrequent resume hang on Ivybridge.
Tested on 2 devices with 15k suspend/resume cycles each
Change-Id: I53618bc7966824413f1720a2be3cbd2550e29473
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1704
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/smi.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index bd4d32c135..bd88df2066 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -269,6 +269,11 @@ static void smm_relocate(void) gpe0_en &= ~PME_B0_EN; outl(gpe0_en, pmbase + GPE0_EN); + pm1_en = 0; + pm1_en |= PWRBTN_EN; + pm1_en |= GBL_EN; + outw(pm1_en, pmbase + PM1_EN); + /* Enable SMI generation: * - on TCO events * - on APMC writes (io 0xb2) @@ -301,11 +306,6 @@ static void smm_relocate(void) outl(smi_en, pmbase + SMI_EN); - pm1_en = 0; - pm1_en |= PWRBTN_EN; - pm1_en |= GBL_EN; - outw(pm1_en, pmbase + PM1_EN); - /** * There are several methods of raising a controlled SMI# via * software, among them: |