src: Get rid of unneeded whitespace

Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

24 files changed, 37 insertions, 37 deletions

diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl
index 9f5033d759..a068bc039c 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pch.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl
@@ -202,7 +202,7 @@ Scope(\)
 		Offset(0x1000), // Chipset
 		Offset(0x3000), // Legacy Configuration Registers
 		Offset(0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select
+		HPAS, 2,	// Address Select
 		, 5,
 		HPTE, 1,	// Address Enable
 		Offset(0x3418), // FD (Function Disable)
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index f95a0b46a0..b0f2a6e90b 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -292,7 +292,7 @@ typedef struct {
 typedef struct {
 	u16  lock_state		     : 1;
 	u16  authenticate_module     : 1;
-	u16  s3authentication  	     : 1;
+	u16  s3authentication	     : 1;
 	u16  flash_wear_out          : 1;
 	u16  flash_variable_security : 1;
 	u16  wwan3gpresent	     : 1;
@@ -350,7 +350,7 @@ typedef struct {
 typedef  struct {
 	u32  mbp_size	 : 8;
 	u32  num_entries : 8;
-	u32  rsvd      	 : 16;
+	u32  rsvd	 : 16;
 } __packed mbp_header;
 
 typedef struct {
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index e2ff851e42..622153cc1e 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -188,7 +188,7 @@ void southbridge_smi_monitor(void)
 			data = RCBA32(0x1e18);
 			data &= mask;
 			// if (smi1)
-			// 	southbridge_smi_command(data);
+			//	southbridge_smi_command(data);
 			// return;
 		}
 		// Fall through to debug
diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c
index d591bccf00..ea48d9e050 100644
--- a/src/southbridge/intel/common/pciehp.c
+++ b/src/southbridge/intel/common/pciehp.c
@@ -46,11 +46,11 @@ void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number)
 			/*
 			  Device (SLOT)
 			  {
-			  	Name (_ADR, 0x00)
-			  	Method (_RMV, 0, NotSerialized)
-			  	{
-			  		Return (0x01)
-			  	}
+				Name (_ADR, 0x00)
+				Method (_RMV, 0, NotSerialized)
+				{
+					Return (0x01)
+				}
 			  }
 			*/
 
diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c
index 99608dc10f..de4ff91cfd 100644
--- a/src/southbridge/intel/common/smbus.c
+++ b/src/southbridge/intel/common/smbus.c
@@ -54,7 +54,7 @@
 #define SMBHSTSTS_HOST_BUSY	(1 << 0)
 
 #define SMBUS_TIMEOUT		(10 * 1000 * 100)
-#define SMBUS_BLOCK_MAXLEN 	32
+#define SMBUS_BLOCK_MAXLEN	32
 
 static void smbus_delay(void)
 {
diff --git a/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl b/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl
index 114aea6021..510749175b 100644
--- a/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl
+++ b/src/southbridge/intel/fsp_bd82x6x/acpi/pch.asl
@@ -202,7 +202,7 @@ Scope(\)
 		Offset(0x1000), // Chipset
 		Offset(0x3000), // Legacy Configuration Registers
 		Offset(0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select
+		HPAS, 2,	// Address Select
 		, 5,
 		HPTE, 1,	// Address Enable
 		Offset(0x3418), // FD (Function Disable)
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.h b/src/southbridge/intel/fsp_bd82x6x/me.h
index f95a0b46a0..b0f2a6e90b 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.h
+++ b/src/southbridge/intel/fsp_bd82x6x/me.h
@@ -292,7 +292,7 @@ typedef struct {
 typedef struct {
 	u16  lock_state		     : 1;
 	u16  authenticate_module     : 1;
-	u16  s3authentication  	     : 1;
+	u16  s3authentication	     : 1;
 	u16  flash_wear_out          : 1;
 	u16  flash_variable_security : 1;
 	u16  wwan3gpresent	     : 1;
@@ -350,7 +350,7 @@ typedef struct {
 typedef  struct {
 	u32  mbp_size	 : 8;
 	u32  num_entries : 8;
-	u32  rsvd      	 : 16;
+	u32  rsvd	 : 16;
 } __packed mbp_header;
 
 typedef struct {
diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c
index 14637e62b3..22489040ae 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smi.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smi.c
@@ -324,7 +324,7 @@ void southbridge_clear_smi_status(void)
 	reset_pm1_status();
 
 	/* Set EOS bit so other SMIs can occur. */
- 	smi_set_eos();
+	smi_set_eos();
 }
 
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index 90ed943cba..c868ec6cf8 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -659,7 +659,7 @@ static void southbridge_smi_monitor(void)
 			data = RCBA32(0x1e18);
 			data &= mask;
 			// if (smi1)
-			// 	southbridge_smi_command(data);
+			//	southbridge_smi_command(data);
 			// return;
 		}
 		// Fall through to debug
diff --git a/src/southbridge/intel/fsp_i89xx/acpi/pch.asl b/src/southbridge/intel/fsp_i89xx/acpi/pch.asl
index f2015d3342..7036f33caa 100644
--- a/src/southbridge/intel/fsp_i89xx/acpi/pch.asl
+++ b/src/southbridge/intel/fsp_i89xx/acpi/pch.asl
@@ -202,7 +202,7 @@ Scope(\)
 		Offset(0x1000), // Chipset
 		Offset(0x3000), // Legacy Configuration Registers
 		Offset(0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select
+		HPAS, 2,	// Address Select
 		, 5,
 		HPTE, 1,	// Address Enable
 		Offset(0x3418), // FD (Function Disable)
diff --git a/src/southbridge/intel/fsp_i89xx/me.h b/src/southbridge/intel/fsp_i89xx/me.h
index f95a0b46a0..b0f2a6e90b 100644
--- a/src/southbridge/intel/fsp_i89xx/me.h
+++ b/src/southbridge/intel/fsp_i89xx/me.h
@@ -292,7 +292,7 @@ typedef struct {
 typedef struct {
 	u16  lock_state		     : 1;
 	u16  authenticate_module     : 1;
-	u16  s3authentication  	     : 1;
+	u16  s3authentication	     : 1;
 	u16  flash_wear_out          : 1;
 	u16  flash_variable_security : 1;
 	u16  wwan3gpresent	     : 1;
@@ -350,7 +350,7 @@ typedef struct {
 typedef  struct {
 	u32  mbp_size	 : 8;
 	u32  num_entries : 8;
-	u32  rsvd      	 : 16;
+	u32  rsvd	 : 16;
 } __packed mbp_header;
 
 typedef struct {
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index 3658a82d4c..0ef7ba8ffb 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -659,7 +659,7 @@ static void southbridge_smi_monitor(void)
 			data = RCBA32(0x1e18);
 			data &= mask;
 			// if (smi1)
-			// 	southbridge_smi_command(data);
+			//	southbridge_smi_command(data);
 			// return;
 		}
 		// Fall through to debug
diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
index 696a81ae65..b55bd92dd1 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
+++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl
@@ -208,7 +208,7 @@ Scope(\)
 		Offset(0x1000), // Chipset
 		Offset(0x3000), // Legacy Configuration Registers
 		Offset(0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select
+		HPAS, 2,	// Address Select
 		, 5,
 		HPTE, 1,	// Address Enable
 		Offset(0x3418), // FD (Function Disable)
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 3a08daad3f..b2b4662f60 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -542,7 +542,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
 			data = RCBA32(0x1e18);
 			data &= mask;
 			// if (smi1)
-			// 	southbridge_smi_command(data);
+			//	southbridge_smi_command(data);
 			// return;
 		}
 		// Fall through to debug
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl
index 8a9aff4a48..cf158df729 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl
@@ -129,7 +129,7 @@ Scope(\)
 		Offset(0x1000), // Chipset
 		Offset(0x3000), // Legacy Configuration Registers
 		Offset(0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select
+		HPAS, 2,	// Address Select
 		, 5,
 		HPTE, 1,	// Address Enable
 		Offset(0x3418), // FD (Function Disable)
diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl
index 143ecb1f2d..52b263f3eb 100644
--- a/src/southbridge/intel/i82801ix/acpi/ich9.asl
+++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl
@@ -132,7 +132,7 @@ Scope(\)
 		Offset(0x1000), // Chipset
 		Offset(0x3000), // Legacy Configuration Registers
 		Offset(0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select
+		HPAS, 2,	// Address Select
 		, 5,
 		HPTE, 1,	// Address Enable
 		Offset(0x3418), // FD (Function Disable)
diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl
index da8b789baa..985e8b657a 100644
--- a/src/southbridge/intel/i82801jx/acpi/ich10.asl
+++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl
@@ -132,7 +132,7 @@ Scope(\)
 		Offset(0x1000), // Chipset
 		Offset(0x3000), // Legacy Configuration Registers
 		Offset(0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select
+		HPAS, 2,	// Address Select
 		, 5,
 		HPTE, 1,	// Address Enable
 		Offset(0x3418), // FD (Function Disable)
diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c
index 35e79c6064..f4382d74f1 100644
--- a/src/southbridge/intel/i82801jx/smihandler.c
+++ b/src/southbridge/intel/i82801jx/smihandler.c
@@ -402,7 +402,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
 			data = RCBA32(0x1e18);
 			data &= mask;
 			// if (smi1)
-			// 	southbridge_smi_command(data);
+			//	southbridge_smi_command(data);
 			// return;
 		}
 		// Fall through to debug
diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h
index 84ae47d3ef..1fe40b6e6f 100644
--- a/src/southbridge/intel/i82870/82870.h
+++ b/src/southbridge/intel/i82870/82870.h
@@ -16,9 +16,9 @@
 #define ABAR		0x40
 
 /* for pci bridge  1460 */
-#define MTT	  	0x042
-#define HCCR	  	0x0f0
-#define ACNF	  	0x0e0
+#define MTT		0x042
+#define HCCR		0x0f0
+#define ACNF		0x0e0
 #define STRP		0x44		// Strap status register
 
 #define STRP_EN133	0x0001		// 133 MHz-capable (Px_133EN)
diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h
index d62b22ad5e..6423d8d29d 100644
--- a/src/southbridge/intel/ibexpeak/me.h
+++ b/src/southbridge/intel/ibexpeak/me.h
@@ -191,7 +191,7 @@ struct mei_header {
 #define MKHI_MDES_ENABLE	0x09
 
 #define MKHI_GET_FW_VERSION	0x02
-#define MKHI_SET_UMA  	        0x08
+#define MKHI_SET_UMA	        0x08
 #define MKHI_END_OF_POST	0x0c
 #define MKHI_FEATURE_OVERRIDE	0x14
 
@@ -293,7 +293,7 @@ typedef struct {
 typedef struct {
 	u16  lock_state		     : 1;
 	u16  authenticate_module     : 1;
-	u16  s3authentication  	     : 1;
+	u16  s3authentication	     : 1;
 	u16  flash_wear_out          : 1;
 	u16  flash_variable_security : 1;
 	u16  wwan3gpresent	     : 1;
@@ -351,7 +351,7 @@ typedef struct {
 typedef  struct {
 	u32  mbp_size	 : 8;
 	u32  num_entries : 8;
-	u32  rsvd      	 : 16;
+	u32  rsvd	 : 16;
 } __packed mbp_header;
 
 typedef struct {
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl
index fbbd26d66f..eaa2690765 100644
--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl
@@ -45,7 +45,7 @@ Scope(\)
 		Offset(0x1000), // Chipset
 		Offset(0x3000), // Legacy Configuration Registers
 		Offset(0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select
+		HPAS, 2,	// Address Select
 		, 5,
 		HPTE, 1,	// Address Enable
 		Offset(0x3418), // FD (Function Disable)
diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h
index a1987eb55e..cef2e55a24 100644
--- a/src/southbridge/intel/lynxpoint/me.h
+++ b/src/southbridge/intel/lynxpoint/me.h
@@ -374,7 +374,7 @@ void intel_me8_finalize_smm(void);
 typedef  struct {
 	u32  mbp_size	 : 8;
 	u32  num_entries : 8;
-	u32  rsvd      	 : 16;
+	u32  rsvd	 : 16;
 } __packed mbp_header;
 
 typedef struct {
@@ -459,7 +459,7 @@ typedef struct {
 typedef struct {
 	u16  lock_state		     : 1;
 	u16  authenticate_module     : 1;
-	u16  s3authentication  	     : 1;
+	u16  s3authentication	     : 1;
 	u16  flash_wear_out          : 1;
 	u16  flash_variable_security : 1;
 	u16  reserved		     : 11;
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 70f2834cd0..ae996e866e 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -392,8 +392,8 @@ void pch_enable_lpc(void);
 #define  XHCI_USB3_PORTSC_WDE	(1 << 26)	/* Wake on Disconnect */
 #define  XHCI_USB3_PORTSC_WOE	(1 << 27)	/* Wake on Overcurrent */
 #define  XHCI_USB3_PORTSC_WRC	(1 << 19)	/* Warm Reset Complete */
-#define  XHCI_USB3_PORTSC_LWS  	(1 << 16)	/* Link Write Strobe */
-#define  XHCI_USB3_PORTSC_PED 	(1 << 1)	/* Port Enabled/Disabled */
+#define  XHCI_USB3_PORTSC_LWS	(1 << 16)	/* Link Write Strobe */
+#define  XHCI_USB3_PORTSC_PED	(1 << 1)	/* Port Enabled/Disabled */
 #define  XHCI_USB3_PORTSC_WPR	(1UL << 31)	/* Warm Port Reset */
 #define  XHCI_USB3_PORTSC_PLS	(0xf << 5)	/* Port Link State */
 #define   XHCI_PLSR_DISABLED	(4 << 5)	/* Port is disabled */
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 5cdd99d431..87848c23c7 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -450,7 +450,7 @@ static void southbridge_smi_monitor(void)
 			data = RCBA32(0x1e18);
 			data &= mask;
 			// if (smi1)
-			// 	southbridge_smi_command(data);
+			//	southbridge_smi_command(data);
 			// return;
 		}
 		// Fall through to debug